IEEE 2014 Projects

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VLSI IEEE 2014 PROJECTS

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  • Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing-2002
  • DCT-Based Image Watermarking Using Subsampling-2003
  • Shift Invert Coding (SINV) for Low Power VLSI-2004
  • Robust DWT-SVD Domain Image Watermarking: Embedding Data in All Frequencies-2004
  • Digital Design of DS-CDMA Transmitter Using VHDL and FPGA-2005
  • Design of Edge Detection Systems
  • A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)-2005
  • A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture-2006
  • An FPGA-based Architecture for Real Time Image Feature Extraction-2004
  • Image Compression with Different Types of Wavelets-2006
2007 Topics
  • A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier
  • Low-power and high-quality Cordic-based Loeffler DCT for signal processing
  • Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
  • A Low-Power Multiplier With the Spurious Power Suppression Technique
  • FPGA Implementation(s) of a Scalable Encryption Algorithm
  • VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application
2008 Topics
  • Fuzzy based PID Controller using VHDL for Transportation Application
  • Research on Fast Super-resolution Image Reconstruction Base on Image Sequence
  • A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
  • FPGA Implementation Of Usb Transceiver Macrocell Interface With USB2.0 Specifications
  • Multiplier design based on ancient Indian Vedic Mathematics
  • A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
  • Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications
  • Implementation of IEEE 802.11 a WLAN Baseband Processor
2009 Topics
  • The CSI Multimedia Architecture
  • Design and Implementation of Boundary-Scan Circuit for FPGA
  • Hardware Algorithm for Variable Precision Multiplication on FPGA
  • VLSI Implementations of the Cryptographic Hash Functions MD6 and ├»rRUPT
  • VLSI Implementation of an Edge-Oriented Image Scaling Processor
  • FPGA-Based Face Detection System Using Haar Classifiers
  • An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM-Convolutional Encoders
  • Fast Scaling in the Residue Number System
  • VLSI Architecture and Chip for Combined Invisible Robust Watermarking
  • Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
  • An Area-Efficient Universal Cryptography Processor for Smart Cards
  • FPGA Based Power Efficient Channelizer for Software Defined Radio
  • Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
  • Lossless Compression using Efficient Encoding of Bitmasks
  • 3D Discrete Wavelet Transform VLSI Architecture for Image Processing
  • A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
2010 Topics
  • Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
  • A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
  • A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
  • FPGA Implementations of the Hummingbird Cryptographic Algorithm
  • FPGA Implementation(s) of a Scalable Encryption Algorithm
  • A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
  • Contrast Enhancement of Color Images using Tunable Sigmoid Function
  • Image Compression with Different Types of Wavelets
  • Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms using Xilinx System Generator.
  • Design and FPGA Implementation of Modular Multiplication methods using Cellular Automata
  • Image Edge Detection Based on FPGA
  • VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN
  • Improvisation of Gabor Filter design using Verilog HDL
  • Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
  • A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
  • VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for JPEG
2011 Topics
  • An Efficient Implementation of Floating Point Multiplier
  • High Speed and Low Space Complexity FPGA Based ECC Processor
  • A blind digital watermarking algorithm based on wavelet transform
  • Design and Simulation of UART Serial Communication Module Based on VHDL
  • Design and VLSI implementation of high-performance face-detection engine for mobile applications
  • Design and Implementation of Area-optimized AES based on FPGA
  • Design of Low Power And High Speed Configurable Booth Multiplier
  • Face detection and recognition method based on skin color and depth information
  • High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
  • A New Reversible Design of BCD Adder
  • Digital Image Authentication from JPEG Headers
  • Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
  • Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
  • A Very Fast and Low Power Carry Select Adder Circuit
  • A_multichannel watermaking scheme based on DCT-DWT
  • An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
  • Design and Characterization of Parallel Prefix Adders using FPGAs
  • FPGA based FFT Algorithm Implementation in WiMAX Communications System
  • FPGA Design of AES Core Architecture for Portable Hard Disk
  • FPGA Implementation of RS232 to Universal serial bus converter
  • Image Encryption Based On AES Key Expansion
  • Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
  • An Efficient Architecture Design for VGA Monitor Controller
  • Curve Fitting Algorithm FPGA implementation
  • FPGA Implementation of AES Algorithm
  • Design of Low Power Column Bypass Multiplier using FPGA
  • Design of Serial Communication Interface Based on FPGA
  • Design and Implementation of an FPGA-based Real-Time Face Recognition System
  • VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders
  • Low Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
  • Design of Low Power And High Speed Configurable Booth Multiplier
  • Design Enhancement Of combinational Neural Networks using HDL Based FPGA framework for Pattern Recognition
  • Efficient VLSI Architecture for Discrete Wavelet Transform
2012 Topics
  • Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits
  • Design of Low Power High Speed VLSI Adder Subsystem
  • Synthesis and Implementation of UART using VHDL Codes
  • HICPA: A Hybrid Low Power Adder for High-Performance Processors
  • Low-Power and Area-Efficient Carry Select Adder
  • Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
  • Design and Implementation of a High Performance Multiplier using HDL
  • Design of Low-Power and High Performance Radix-4 Multiplier
  • Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
  • FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers
  • High Speed and Area Efficient Vedic Multiplier
  • High speed Modified Booth Encoder multiplier for signed and unsigned numbers
  • An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
  • High Speed Signed Multiplier for Digital Signal Processing Applications
  • Accumulator Based 3-Weight Pattern Generation
  • Design of Low Power TPG Using LP-LFSR
  • Viterbi-Based Efficient Test Data Compression
  • A Feature-Based Robust Digital Image Watermarking Scheme
  • Digital Image Watermarking Based on Super Resolution Image Reconstruction
  • Hardware Implementation of a Digital Watermarking System for Video Authentication
  • Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code
  • Watermarking Scheme for Copyright Protection of 3d Animated Model
  • Efficiency of BCH Codes in Digital Image Watermarking
  • Image Magnification by Modifying DCT Coefficients
  • A Real-time Face Detection And Recognition System
  • VHDL Implementation of UART with Status Register
  • Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC
  • FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
  • Pipelined Parallel FFT Architectures via Folding Transformation
  • VHDL Design for Image Segmentation using Gabor filter for Disease Detection.
  • An Efficient Viterbi Decoder
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • Very Low Resolution Face Recognition Problem
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
2013 Topics
  • 16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder
  • Area-Delay Efficient Binary Adders in QCA
  • Asynchronous Design of Energy Efficient Full Adder
  • Comments on “Low-Energy CSMT Carry Generators and Binary Adders”
  • FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder
  • Low-Power Digital Signal Processing Using Approximate Adders
  • Design of High Speed Low Power Multiplier using Reversible logic-A Vedic Mathematical Approach
  • FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter
  • Novel High Speed Vedic Mathematics Multiplier using Compressors
  • Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
  • A Robust QR- Code Video Watermarking Scheme Based On SVD and DWT Composite Domain
  • A Wavelet based Image Watermarking Technique using Image Sharing Method
  • An Adaptive Blind Video Watermarking Technique based on SD-BPSO and DWT-SVD
  • Digital watermarking using DWT and DES
  • Digital Watermarking with copyright authentication for image communication
  • Hardware Implementation of a Digital Watermarking System for Video Authentication
  • Image authentication and restoration by multiple watermarking techniques with advance encryption standard in digital photography
  • Implementation and performance analysis of DCT-DWT-SVD based watermarking algorithms for colour images
  • Robust Watermarking of AES Encrypted Images for DRM Systems
  • A Fatigue Detection System with Eyeglasses Removal
  • A Novel Approach for Face Detection using Artificial Neural Network
  • Children Detection Algorithm Based on Statistical Models and LDA in Human Face Images
  • Efficient algorithms for detection of face, eye and eye state
  • A 2D Discrete Wavelet Transform Based 7-State Hidden Markov Model for Efficient Face Recognition
  • Analysis of Multispectral Image Using Discrete Wavelet Transform
  • Discrete Wavelet Transform and Data Expansion Reduction in Homomorphic Encrypted Domain
  • Image steganography in DWT domain using double-stegging with RSA encryption
  • Study and Analysis of PCA, DCT & DWT based Image Fusion Techniques
  • Texture classification using color local texture features
  • VLSI architecture of multiplier-less DWT image processor
  • VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor
  • Multiplier-less VLSI architecture of 1-D Hilbert transform pair using Biorthogonal Wavelets
  • VLSI implementation of low-power cost-efficient lossless ECG encoder design for wireless healthcare monitoring application 
2014 Topics
  • Distributed Canny Edge Detector Algorithm and FPGA Implementation
  • Area-Delay-Power Efficient Carry-Select Adder
  • Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
  • Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
  • Area-Delay Efficient Binary Adders in QCA
  • Efficient Integer DCT Architectures for HEVC
  • Recursive Approach to the Design of a Parallel Self-Timed Adder
    Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
  • High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
  • Comments on Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding
  • Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform
  • A Decimal  Binary Multi-operand Adder using a Fast Binary to Decimal Converter
  • ASIC Design of Reversible Multiplier Circuit
  • A Novel MRI Brain Edge Detection Using PSOFCM Segmentation and Canny Algorithm
  • Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder
  • Real Time Human Face Detection and Tracking
  • Key Dependent Image Steganography Using Edge Detection
  • High-Throughput Programmable Systolic Array FFT Architecture and FPGA Implementations
  • VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications
  • Area–Delay–Power Efficient Carry-Select Adder
  • Block Based Robust Blind Image Watermarking Using Discrete Wavelet Transform
  • Gabor Filter Based Hand-Drawn Underline Removal in Printed Documents
  • A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL
  • Design of Low Power Split Path Data Driven Dynamic Ripple Carry Adders
  • Pipelined Architecture for Vedic Multiplier
  • Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic
  • Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation
  • Transaction-based SoC Design Techniques for AMBA AXI4 Bus Interconnects using VHDL
  • High Speed Convolution and Deconvolution Algorithm
  • Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
  • Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
  • Recursive Approach to the Design of a Parallel Self-Timed Adder
  • A Novel Architecture for QPSK Modulation based on Time-Mode Signal Processing
  • A Positive Level Shifter for High Speed Symmetric Switching in Flash Memories
  • An Efficient Hardware Architecture for Stereo Disparity Estimation
  • An Approach for Efficient FIR Filter Design for Hearing Aid Application
  • An Efficient Algorithm for Power and Delay Minimization in on-chip Bus
    The above listed topics are just for reference. If you have any new Ideas/Papers send to us at info@verilogcourseteam.com or Call +91 98942 20795.
     


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