tag:blogger.com,1999:blog-18283509597844091262016-01-18T16:28:01.892+05:30VLSI IEEE Projects in ChennaiVLSI IEEE 2015 Projects in Chennai.http://www.blogger.com/profile/12231586279374897112noreply@blogger.comBlogger63125tag:blogger.com,1999:blog-1828350959784409126.post-11962368144107961012016-01-18T16:30:00.000+05:302016-01-18T16:28:01.924+05:30VLSI IEEE 2015 PROJECT @Chennai<div dir="ltr" style="text-align: left;" trbidi="on"><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b> VLSI PROJECT TOPICS </b></span></div><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2003</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">DCT-Based Image Watermarking Using Subsampling- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of Invisible Digital Watermarking Algorithms- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2004</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An FPGA-based Architecture for Real Time Image Feature Extraction- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Contrast Enhancement of Color Images using Tunable Sigmoid Function- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Robust DWT-SVD Domain Image Watermarking Embedding Data in All Frequencies</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Shift Invert Coding (SINV) for Low Power VLSI</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of Discrete Wavelet Transform (DWT) and IDWT for Image Compression- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2005</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Visual Attention Driven Image to Video Adaptation- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2006</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Verilog Implementation of UART Design with BIST Capability</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Image Compression with Different Types of Wavelets- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2007</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Low-Power Multiplier With the Spurious Power Suppression Technique</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Implementation of a low complexity real lossless Image compression method for wireless endoscopy capture system- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Low-power and high-quality Cordic-based Loefﬂer DCT for signal processing</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Low-Power Built-In Logic Block Observer Realization for BIST Applications-VHDL</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Video Adaptation for Small Display Based on Content Recomposition- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2008</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Based Design of a Novel Enhanced Error Detection And Correction Technique</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of a Scalable Encryption Algorithm</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Fuzzy based PID Controller using Verilog HDL for Transportation Application</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Implementation of 64 Point FFT using Vedic Multiplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Implementation of IEEE 802.11 a WLAN Baseband Processor</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Multiplier design based on ancient Indian vedic muliplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Research on Fast Super-resolution Image Reconstruction Base on Image Sequence-Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of an Edge-Oriented Image Scaling Processor- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2009</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">3D Discrete Wavelet Transform VLSI Architecture for Image Processing- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM- Convolutional Encoders</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Biometric Encryption using Fingerprint Fuzzy Vault for FPGA-based Embedded Systems- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">CSI Multimedia Architecture</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Fast Scaling in the Residue Number System</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Implementation of Boundary-Scan Circuit</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Based Power Efficient Channelizer For Software Defined Radio</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA-Based Face Detection System Using Haar Classifiers- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Hardware Algorithm for Variable Precision Multiplication on FPGA</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementations of the Cryptographic Hash Functions MD6</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2010</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementations of the Hummingbird Cryptographic Algorithm</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A High-speed 32-bit Signed Unsigned Pipelined Multiplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Software-Defined Radio for OFDM Transceivers</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of Fully Pipelined Multiplier less 2D DCT IDCT Architecture for JPEG- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">High Speed and Low Space Complexity FPGA Based ECC</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of Modular Multiplication methods using Cellular Automata</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of High Performance LDPC Decoder using Modified 2-bit</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of Low-Power High-Speed Truncation-Error-Tolerant Adder</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Coherent Amplitude Modulated QAM-QPSK</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modiﬁed Booth Algorithm</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264AVC- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A High Performance Binary to BCD Converter for Decimal Multiplication</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2011</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A New Reversible Design of BCD Adder</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Multichannel Watermarking DCT-DWT- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An Efficient Implementation of Floating Point Multiplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An implementation of a 2D FIR filter using the signed-digit number system- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Automatic Road Extraction using High Resolution Satellite Images based on Mean Shift Method- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Implementation of APB Bridge based on AMBA 4.0</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and VLSI implementation of high-performance face-detection engine for mobile applications- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design Enhancement of Combinational Neural Networks Using HDL based FPGA Framework for Pattern Recognition- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Efficient VLSI Architecture for Discrete Wavelet Transform- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA based FFT Algorithm Implementation in WiMAX Communications System</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise Two Approaches- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Image Encryption Based On AES Key Expansion- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">PCFICH Channel Design for LTE using FPGA- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Pipelined Architecture for FPGA Implementation of Lifting-Based DWT- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2012</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Region Merging Approach for Image Segmentation on FPGA- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">An Efficient Viterbi Decoder</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of Low Power TPG Using LP-LFSR</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">HDL Design for Image Segmentation using Gabor filter for Disease Detection- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">High Speed and Area Efficient Vedic Multiplier</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Improved Architectures for a Fused Floating-Point Add-Subtract Unit</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Low-Power and Area-Efficient Carry Select Adder</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Low-Power Variation-Aware Flip Flop</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Modified Architecture for Real-Time Face Detection using FPGA- VHDL with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Very Low Resolution Face Recognition Problem- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Viterbi-Based Efficient Test Data Compression</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Architecture of Arithmetic Coder Used in SPIHT- Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2013</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Cordic for Fixed Angle Rotation</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design Of High Speed Floating Point Mac Using Vedic Multiplier And Parallel Prefix Adder</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of High Speed Low Power Multiplier using Reversible logic-a Vedic Mathematical Approach</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design of High-speed low power Reversible Logic BCD Adder Using HNG gate</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Techniques for Compensating Memory Errors in JPEG2000- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Visible and Infrared Image Fusion using the Lifting Wavelets- VHDL with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of an Adaptive Edge -Enhanced Image Scalar for RealTime Multimedia Applications- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform Neural Network Architecture- </span><span style="font-family: "georgia" , "times new roman" , serif;"> </span><span style="font-family: "georgia" , "times new roman" , serif;">Verilog with Matlab</span></li></ul><div style="text-align: justify;"><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2014</b></span></div><ul style="text-align: justify;"><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Distributed Canny Edge Detector Algorithm and FPGA Implementation- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A New Secure Image Transmission Technique via Secret-Fragment-Visible Mosaic Images- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Implementation of Orthogonal Code Convolution Using Enhanced Error Control Technique</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">SW-HW Implementation of Image Covariance Descriptor For Person Detection Systems</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">VLSI Based Image Zooming Application by a Novel Adaptive Edge Enhancement Technique- Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform-Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay-Verilog with Matlab </span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">ASIC Implementation of Two Stage Pipelined Multiplier </span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Hardware Software Co-Simulation of Edge Detection for Image Processing System-Verilog with Matlab</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform-Verilog with Matlab</span></li></ul><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;"><b>2015 </b></span><br /><ul><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Reviewing High-Radix Signed-Digit Adders </span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A New-High Speed-Low Power-Carry Select adder Using Modified GDI</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Modified Partial Product Generator for Redundant Binary Multipliers</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Design and Analysis of Approximate Compressors for Multiplication</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System</span></li><li><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT</span></li></ul><div><ul style="text-align: justify;"></ul><div style="text-align: justify;"><b><span style="font-family: "georgia" , "times new roman" , serif; font-size: small;">The above listed topics are just for reference. If you have any new Ideas/Papers send to us at info@verilogcourseteam.com or Call +91 98942 20795/+9144 42647783</span></b></div></div></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-72416316541862356292009-11-13T15:33:00.002+05:302011-07-15T15:06:08.202+05:30SIMULATION MODEL OF VISIBLE WATERMARKING FOR JPEG IMAGE (3 D) USING VLSI/MATLAB<div style="text-align: justify;"><span style="font-weight: bold;">Watermarking </span>is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This project presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework.<br /><br />Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. The watermarking object may be an image, audio, video, or text .Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection.<br /><br />According to human perception, the digital watermarks can be divided into four categories:<br /><br />1) visible;<br /><br />2) invisible-robust;<br /><br />3) invisible-fragile;<br /><br />4) dual<br /><br />A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark . In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. There are numerous software-based watermarking schemes available in literature. A vast research community involving experts from computer science, cryptography, signal processing, and communications, etc., are working together to develop watermarks that can withstand different possible forms of attacks, each one of which has its own applications and thus is equally important. There is a gap between the image capture and image transmission in thewaywatermarking is used presently. Once the images are acquired,watermarks are inserted in them offline, and then images are made available. The objective of this research work is to implement hardware-based watermarking schemes so as to bridge that gap. The watermark chip will be fitted in the devices that acquire the image and watermark the images in real time while capturing.</div><br /><span style="font-weight: bold;">VIDEO DEMO</span><br /><object width="340" height="285"><param name="movie" value="http://www.youtube.com/v/-hAtIm4Epb0&hl=en&fs=1&rel=0&border=1"><param name="allowFullScreen" value="true"><param name="allowscriptaccess" value="always"><embed src="http://www.youtube.com/v/-hAtIm4Epb0&hl=en&fs=1&rel=0&border=1" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="340" height="285"></embed></object><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com1tag:blogger.com,1999:blog-1828350959784409126.post-27701399249307755652009-11-13T15:09:00.000+05:302009-11-13T15:10:03.906+05:30SIMULATION OF HARDWARE BASED EDGE DETECTION<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION:</span><br /><br />Edge detection is a fundamental tool used in most image processing applications to obtain information from the frames before feature extraction and object segmentation. This process detects outlines of an object and boundaries between objects and the background in the image. Beyond that, Edge Detection refers to the process of identifying and locating sharp discontinuities in intensities in an image. The discontinuities are abrupt changes in pixels intensity which characterize boundaries of objects in a scene structure. This process significantly reduces the amount of date in the image, while preserving the most important structural feature of that image. Edge detection is considered to be the ideal algorithm for images that are corrupted with white noise. The Edge is characterized by its height, slope angle,and horizontal coordinate of the slope midpoint. An ideal Edge Detector should produce an edge indication localized to a single pixel located at the midpoint of the slope.There are many ways to perform Edge detection. However, the majority of different methods may be grouped into two categories, gradient and Laplacian. The basic Edge detection operator is a matrix area gradient operation that determines the level of variance between different pixels. The edge detection operator is calculated by forming a matrix centered on a pixel chosen as the centre of the matrix area. If the value of the matrix area is above a given threshold, then the middle pixel is classified as an edge. Examples of gradient based edge detectors are Roberts, Prewitt and Sobel operators. All the gradient –based algorithms have Kernel operators that calculate the strength of the slope in directions that are orthogonal to each other, generally horizontal and vertical.<br />The requirements that the algorithms must meet are:<br />a) Show the effectiveness and the noise resistance for remote sensing image.<br />b) Satisfying real time-constraints, and minimizing hardware resources in order to meet embedding requirements.<br />c) Significantly reducing the amount of date and filters out useless information.<br /><br />Classically, Edge detection algorithms are implemented on software. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithm yield significant speedup in running times. Implementation image processing on reconfigurable hardware minimizes the time-to-market cost, enables rapid prototyping of complex algorithm and simplifies debugging and verification.<br /><br /><span style="font-weight: bold;">VIDEO DEMO</span><br /></div><br /><object width="425" height="344"><param name="movie" value="http://www.youtube.com/v/ik-HUJckMLo&hl=en&fs=1&"><param name="allowFullScreen" value="true"><param name="allowscriptaccess" value="always"><embed src="http://www.youtube.com/v/ik-HUJckMLo&hl=en&fs=1&" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="425" height="344"></embed></object><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-11932383480801348752009-11-13T15:00:00.000+05:302009-11-13T15:01:05.210+05:30Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor<div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">INTRODUCTION</span><br /></div><div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate: </div><div style="text-align: justify;">1) parallelizing the scrambler function and </div><div style="text-align: justify;">2) concatenating the FEC encoder, puncturing, and inter leaver functions.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">802.11A DIGITAL BASEBAND TRANSMITTER</span></div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">Table 1 lists the mode-dependent parameters for the 802.11a standard.</div></div></div><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://3.bp.blogspot.com/_D3t0yzWw-mU/SU_UEHfNFRI/AAAAAAAAAKA/GxNl1vtMR6o/s1600-h/1.bmp"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 400px; height: 186px;" src="http://3.bp.blogspot.com/_D3t0yzWw-mU/SU_UEHfNFRI/AAAAAAAAAKA/GxNl1vtMR6o/s400/1.bmp" alt="" id="BLOGGER_PHOTO_ID_5282674055123375378" border="0" /></a><div style="text-align: justify;">The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol. <span class="Apple-tab-span" style="white-space: pre;"> </span><br /></div><div style="text-align: justify;"><br /></div><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://1.bp.blogspot.com/_D3t0yzWw-mU/SU_S6q7NuRI/AAAAAAAAAJ4/4zO33WFD6IE/s1600-h/1.bmp" style="text-decoration: none;"><img style="margin: 0px auto 10px; text-decoration: underline; text-align: justify; display: block; cursor: pointer; width: 400px; height: 199px;" src="http://1.bp.blogspot.com/_D3t0yzWw-mU/SU_S6q7NuRI/AAAAAAAAAJ4/4zO33WFD6IE/s400/1.bmp" alt="" id="BLOGGER_PHOTO_ID_5282672793325779218" border="0" /></a><div style="text-align: justify;"><br /></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;"><br /></span><br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-42114634612084376152009-11-13T14:53:00.002+05:302009-11-13T14:57:07.968+05:30A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I COMPRESSION ALGORITHM<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />One of the most challenging test stands for wearable computer and remote sensor systems is the transmission of images. In fact, the amount of memory needed for the storage of color video images and the high speed required for their transmissions make the performance/ cost tradeoff difficult to attain. As a consequence, compression techniques are mandatory to sensibly reduce the amount of data needed for frame transmission. As far as static images are concerned,1 the best performance and compression rates are obtained by lossy algorithms, such as JPEG or JPEG2000. However, specific applications may prefer low-complex lossless schemes, especially if the quality of the transmitted image is a mandatory constraint. Among all others, Lossless JPEG , FELICS, and CALIC are few examples of lossless compression algorithms, but the coding scheme that features the best complexity/compression rate tradeoff is LOCO-I (low complexity lossless compression for images), the core of the JPEG-LS standard.<br /><br />In this project, we present an efficient implementation of the LOCO-I algorithm tailored for field-programmable gate-array (FPGA) applications. The design takes fully advantage of the sequential nature of the LOCO-I compression scheme and results into a pipelined architecture for both encoder and decoder circuits. Consequently, significant performance improvements can be obtained with respect to previous nonpipelined designs without modifying the original compression scheme. <a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://3.bp.blogspot.com/_D3t0yzWw-mU/Sv0mMwqcTDI/AAAAAAAAAQA/DUI6_vhH2P8/s1600-h/1.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 397px; height: 399px;" src="http://3.bp.blogspot.com/_D3t0yzWw-mU/Sv0mMwqcTDI/AAAAAAAAAQA/DUI6_vhH2P8/s400/1.jpg" alt="" id="BLOGGER_PHOTO_ID_5403517128577666098" border="0" /></a></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-2700258011763565142009-11-13T14:50:00.002+05:302009-11-13T14:53:30.430+05:30VLSI IMPLEMENTATION OF AN EDGE-ORIENTED IMAGE SCALING PROCESSOR<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />IMAGE scaling is widely used in many fields, ranging from consumer electronics to medical imaging. It is indispensable when the resolution of an image generated by a source device is different from the screen resolution of a target display. For example, we have to enlarge images to fit HDTV or to scale them down to fit the mini-size portable LCD panel. The most simple and widely used scaling methods are the nearest neighbor and bilinear techniques. In recent years, many efficient scaling methods have been proposed in the literature.<br /><br />According to the required computations and memory space, we can divide the existing scaling methods into two classes: lower complexity and higher complexity scaling techniques. The complexity of the former is very low and comparable to conventional bilinear method. The latter yields visually pleasing images by utilizing more advanced scaling methods. In many practical real-time applications, the scaling process is included in end-user equipment, so a good lower complexity scaling technique, which is simple and suitable for low-cost VLSI implementation, is needed. In this project, we consider the lower complexity scaling techniques only. Kim presented a simple area-pixel scaling method. It uses an area-pixel model instead of the common point-pixel model and takes a maximum of four pixels of the original image to calculate one pixel of a scaled image. By using the area coverage of the source pixels from the applied mask in combination with the difference of luminosity among the source pixels, Andreadis proposed a modified area-pixel scaling algorithm and its circuit to obtain better edge preservation. Both obtain better edge-preservation but require about two times more of computations than the bilinear method. To achieve the goal of lower cost, we present an edge-oriented area-pixel scaling processor in this paper. The area-pixel scaling technique is approximated and implemented with the proper and low-cost VLSI circuit in our design. The proposed scaling processor can support floating-point magnification factor and preserve the edge features efficiently by taking into account the local characteristic existed in those available source pixels around the target pixel. Furthermore, it handles streaming data directly and requires only small amount of memory: one line buffer rather than a full frame buffer. The experimental results demonstrate that the proposed design performs better than other lower complexity image scaling methods in terms of both quantitative evaluation and visual quality. </div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-42579496803745735612009-11-13T14:47:00.002+05:302009-11-13T14:49:43.403+05:30DIGITAL DESIGN OF DS-CDMA TRANSMITTER USING VERILOG AND FPGA<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />In recent years, there has been a significant amount of research performed in both industry and academia into the development of CDMA systems. A clear description of a CDMA has been elusive, since it has a different meaning to every researcher involved in the topic. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, being distinguished by the use of different spreading codes CDMA communication is employed in, for example, digital cellular telephone systems and personal communication services. In these systems, a base station communicates with a plurality of mobile stations, one frequency band being used for all of the up-links from the mobile stations to the base station, and another frequency band being used for all of the down-links from the base station to the mobile stations.<br /><br />This project describes the design and a circuit for pseudo random PN coding and synchronization of a wireless transmitter for DS-CDMA using Verilog HDL. The circuit for the transmitter is comprised of basic digital components, such as flip-flops, oscillators, shift registers, PN coder and a BPSK modulator. XILINX/ALTEAR FPGA to implement this circuit.<br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com1tag:blogger.com,1999:blog-1828350959784409126.post-48346149124303007182009-11-13T14:43:00.002+05:302009-11-13T14:46:46.387+05:30VLSI IMPLEMENTATIONS OF THE CRYPTOGRAPHIC HASH FUNCTIONS MD6 AND ïrRUPT<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />Cryptographic hash functions are ubiquitous algorithm used in numerous schemes like digital signatures, public-key encryption, or MAC's. Hash functions process an arbitrary-length message to produce a small fixed-length digital fingerprint, and should satisfy a variety of security properties (preimage resistance, collision resistance, pseudorandomness, etc.). In the last years, a wide range of attacks have been applied to the previous standards MD5 and SHA-1, to break their collision resistance . Although only collisions in reduced versions of the current standard SHA-2 are known , researchers are skeptical about its long-term security. As a response, the U.S. National Institute of Standards and Technologies (NIST) recently launched a call for candidate functions for a new cryptographic hash algorithm (SHA-3) family . The hash functions MD6 (by the author of MD5) and ïrRUPT have been accepted as Round 1 candidates. Besides a high security, the new hash standard should be suitable for implementations on a wide range of applications. In particular, hardware efficiency will be crucial to determine the future SHA-3, because hardware resources are often limited, whereas on high-end PC's it does not matter much in general; indeed, even the slowest hash function has acceptable performance on a PC. Furthermore, hash function designers seldom study the hardware performance. It is thus necessary to independently study implementations of future candidates on ASIC and FPGA, and determine their suitability for resource limited environments.<br /><br />This project presents a hardware architectures for the hash functions MD6 and ïrRUPT. Particular attention has been drawn in the analysis of the round process to exploit parallelism, to maximize the circuit speed. </div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-8123034825959980142009-11-13T14:40:00.002+05:302009-11-13T14:42:45.269+05:30AN EFFICIENT DIGITAL VLSI IMPLEMENTATION OF GAUSSIAN MIXTURE MODELS-BASED CLASSIFIER<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />THE GAUSSIAN mixture models (GMM) classifier has gained increasing attention in the pattern recognition community. GMM can be classified as a semi-parametric density estimation method since it defines a very general class of functional forms for the density model. In this mixture model, a probability density function is expressed as a linear combination of basis functions. Improved classification performances have been demonstrated in many pattern recognition applications . Performance figures of more than 95% have already been reported for applications such as electronic nose and gas identification. Another interesting property of GMM is that the training procedure is done independently for each class in turn by constructing a Gaussian mixture of a given class. Adding a new class to a classification problem does not require retraining the whole system and does not affect the topology of the classifier making it attractive for pattern recognition applications. While GMM provides very good performances and interesting properties as a classifier, it presents some problems that may limit its practical use in real-time applications. One problem is that GMM can require large amounts of memory to store various coefficients and can require complex computations mainly involving exponential calculations. Thus, this scheme can be put to efficient practical use only if good hardware implementation strategies are developed.<br /><br />In this project, we propose an efficient digital VLSI implementation that we believe can meet the computational requirement of GMM-based classifiers. First, after analyzing the complexity of the GMM classifier it was found that the vector-matrix multiplication and the exponential calculations are the most critical operations in the classifier. A good tradeoff between real-time processing and hardware resources requirements is obtained using a serial-parallel architecture and an efficient pipelining strategy. Second, a linear piecewise function (LPF) is proposed to replace the exponential calculation. Implementing LPF-based GMM, also permits to avoid the need for using area consuming look-up table (generally used in digital implementation) to implement the exponential function. The effect of both limited precision and the mixture models approximation using LPF on the classification performance is investigated using seven different data-sets. These data-sets are also used to compare the performance of GMM with other benchmark classifiers.<br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-4760384576617577002009-11-13T14:37:00.002+05:302009-11-13T14:40:07.053+05:30AN OPTIMUM ORA BIST FOR MULTIPLE FAULT FPGA LOOK-UP TABLE TESTING<div style="text-align: justify;"><span style="font-weight: bold;">Introduction<br /><br /></span>Field Programmable Gate Arrays (FPGAs) have been widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high speed telecommunication chips. FPGAs are suitable for prototypes of systems whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA. The frequent reconfiguration of an FPGA makes it more fault-prone.There are many components of an FPGA to test for ensuring reliable usage of this device.<br /><br />In this projecy, we only consider test of LEs and focus on LUTs within LEs. There are different methods for LE testing. One may use I/O pins for applying test vectors to LEs and collecting test results. But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable . A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing, which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs. Our objective is to propose a BIST architecture with a good balance between various costs. Test time, test area and granularity are such trade-offs. </div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-46903230969137367462009-11-13T14:33:00.002+05:302009-11-13T14:37:00.951+05:30A SYMBOL-RATE TIMING SYNCHRONIZATION METHOD FOR LOW POWER WIRELESS OFDM SYSTEMS<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />TRADEOFF between system performance and power dissipation is one of the most critical issues in the design of a wireless portable device. Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multirate sampling the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm to yield a symbol-rate signal stream for data decoding. This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.<br /><br />To enable power reduction with symbol-rate sampling, both Mueller–Muller detection (MMD) and MMD-based timing recovery methods have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing synchronization issue in orthogonal frequency-division multiplexing (OFDM) systems based on the best block-boundary search for each fast Fourier transform (FFT) window.<br /><br />Accordingly, multirate sampling,schemes have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation. To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sampletiming control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multirate sampling methods, this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC for low-power wireless applications.</div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-63865757360032567992009-11-13T14:26:00.002+05:302009-11-13T14:32:40.803+05:30IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check , others are designed to detect as well as correct errors, such as Salomon Codes. However, the existing techniques are not able to achieve high efficiency and to meet bandwidth requirements, especially with the increase in the quantity of data transmitted.<br /><br />Orthogonal Code is one of the codes that can detect errors and correct corrupted data. Our objective in this paper is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.<br /><br /><span style="font-weight: bold;">ORTHOGONAL CODES</span><br />Orthogonal codes are binary valued and they have equal number of 1’s and 0’s. An n-bit orthogonal code has n/2 1’s and n/2 0’s; i.e., there are n/2 positions where 1’s and 0’s differ . Therefore, all orthogonal codes will generate zero parity bits. The concept is illustrated by means of an 8- bit orthogonal code as shown in Fig.1. It has 8-orthogonal codes and 8-antipodal codes for a total of 16-biorthogonal codes. Antipodal codes are just the inverse of orthogonal codes; they are also orthogonal among themselves.<br /><br /><a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://2.bp.blogspot.com/_D3t0yzWw-mU/Sv0ggd1tDgI/AAAAAAAAAP4/ImN-LRoVbxQ/s1600-h/1.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer; width: 400px; height: 218px;" src="http://2.bp.blogspot.com/_D3t0yzWw-mU/Sv0ggd1tDgI/AAAAAAAAAP4/ImN-LRoVbxQ/s400/1.jpg" alt="" id="BLOGGER_PHOTO_ID_5403510870052244994" border="0" /></a><br /><br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com3tag:blogger.com,1999:blog-1828350959784409126.post-90453126820522067172009-11-13T13:44:00.001+05:302009-11-13T13:46:50.087+05:30FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />Scalable encryption algorithm (SEA) is a parametric block cipher for resource constrained systems (e.g., sensor networks, RFIDs) that has been introduced . It was initially designed as a low-cost encryption/ authentication routine (i.e., with small code size and memory) targeted for processors with a limited instruction set (i.e., AND, OR, XOR gates, word rotation, and modular addition). Additionally and contrary to most recent block ciphers (e.g., the DES and AES Rijndael , the algorithm takes the plaintext, key, and the bus sizes as parameters and, therefore, can be straightforwardly adapted to various implementation contexts and/or security requirements. Compared to older solutions for low-cost encryption like tiny encryption algorithm (TEA) or Yuval’s proposal , SEA also benefits from a stronger security analysis, derived from recent advances in block cipher design/cryptanalysis.<br /><br />In practice, SEA has been proven to be an efficient solution for embedded software applications using microcontrollers, but its hardware performances have not yet been investigated. Consequently, and as a first step towards hardware performance analysis, this letter explores the features of a low-cost field-programmable gate array (FPGA) encryption/ decryption core for SEA. In addition to the performance evaluation, we show that the algorithm’s scalability can be turned into a fully generic VHDL/Verilog design, so that any text, key, and bus size can be straightforwardly reimplemented without any modification of the hardware description language, with standard synthesis and implementation tools.<br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-25532253191730573972009-08-05T16:21:00.011+05:302009-08-05T16:48:10.378+05:30TECHNICAL INFORMATION - ACADEMIC PROJECT<span style=";font-family:georgia;font-size:100%;" >Dear Students,<br /><br />Now you can get Technical Information for your Academic Projects from</span><span style="font-size:100%;"><a href="http://www.verilogcourseteam.com/academic-solutions"><span style="font-weight: bold;"> </span></a><br /><br /><a href="http://www.verilogcourseteam.com/academic-solutions"><span style="font-weight: bold;">http://www.verilogcourseteam.com/academic-solutions</span></a><br /><br /></span><div style="text-align: left;font-family:georgia;"><span style="font-size:100%;">Students can also sent their Ideas with related documents/IEEE Papers to<br /><br /></span><span style="font-size:100%;"><a style="font-weight: bold;" href="mailto:info@verilogcourseteam.com">info@verilogcourseteam.com</a><br /><br />For discussion contact Our Team Member @ +91 98942 20795.<br /><br /><br />--<br />Sincerely<br /><br />Verilog Course Team<br />INDIA<br /><a href="http://www.blogger.com/www.verilogcourseteam.com">www.verilogcourseteam.com</a><br /><br /></span></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-74112292390370255722009-01-12T11:36:00.001+05:302009-06-03T20:21:04.489+05:30ROBUST DWT-SVD DOMAIN IMAGE WATERMARKING:<div><span class="Apple-style-span" style=" ;font-family:'Times New Roman';"><div style="border-top-width: 0px; border-right-width: 0px; border-bottom-width: 0px; border-left-width: 0px; border-style: initial; border-color: initial; margin-top: 0px; margin-right: 0px; margin-bottom: 0px; margin-left: 0px; padding-top: 3px; padding-right: 3px; padding-bottom: 3px; padding-left: 3px; width: auto; font: normal normal normal 100%/normal Georgia, serif; text-align: left; "><div style="text-align: justify; "><span class="Apple-style-span" style="font-weight: bold; ">INTRODUCTION</span></div><div style="text-align: justify; "><span class="Apple-style-span" style="font-weight: bold; "><br /></span></div><div style="text-align: justify; ">Watermarking (data hiding) is the process of embedding data into a multimedia element such as image, audio or video. This embedded data can later be extracted from, or detected in, the multimedia for security purposes. A watermarking algorithm consists of the watermark structure, an embedding algorithm, and an extraction, or a detection, algorithm. Watermarks can be embedded in the pixel domain or a transform domain. In multimedia applications, embedded watermarks should be invisible, robust, and have a high capacity. Invisibility refers to the degree of distortion introduced by the watermark and its affect on the viewers or listeners. Robustness is the resistance of an embedded watermark against intentional attacks, and normal A/V processes such as noise, filtering (blurring, sharpening, etc.), resampling, scaling, rotation, cropping, and lossy compression. Capacity is the amount of data that can be represented by an embedded watermark. The approaches used in watermarking still images include least-significant bit encoding, basic M-sequence, transform techniques, and image-adaptive techniques.An important criterion for classifying watermarking schemes isthe type of information needed by the detector:</div><div style="text-align: justify; "><br /></div><div style="text-align: justify; ">• Non-blind schemes: Both the original image and the secret key(s) for watermark embedding.</div><div style="text-align: justify; ">• Semi-blind schemes: The secret key(s) and the watermarkbit sequence.</div><div style="text-align: justify; ">• Blind schemes: Only the secret key(s).</div><div style="text-align: justify; "><br /></div><div style="text-align: justify; ">Typical uses of watermarks include copyright protection (identification of the origin of content, tracing illegally distributed copies) and disabling unauthorized access to content. Requirements and characteristics for the digital watermarks in these scenarios are different, in general. Identification of the origin of content requires the embedding of a single watermark into the content at the source of distribution. To trace illegal copies, a unique watermark is needed based on the location or identity of the recipient in the multimedia network. In both of these applications, non-blind schemes are appropriate as watermark extraction or detection needs to take place in a special laboratory environment only when there is a dispute regarding the ownership of content. For access control, the watermark should be checked in every authorized consumer device used to receive the content, thus requiring semi-blind or blind schemes. Note that the cost of a watermarking system will depend on the intended use, and may vary considerably. Two widely used image compression standards are JPEG and JPEG2000. The former is based on the Discrete Cosine Transform (DCT), and the latter the Discrete Wavelet Transform (DWT). </div><div style="text-align: justify; "><br /></div><div style="text-align: justify; ">In recent years, many watermarking schemes have been developed using these popular transforms. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.In all frequency domain watermarking schemes, there is a conflict between robustness and transparency. If the watermark is embedded in perceptually most significant components, the scheme would be robust to attacks but the watermark may be difficult to hide. On the other hand, if the watermark is embedded in perceptually insignificant components, it would be easier to hide the watermark but the scheme may be least resistant to attacks. In image watermarking, two distinct approaches have been used to represent the watermark. In the first approach, the watermark is generally represented as a sequence of randomly generated real numbers having a normal distribution with zero mean and unity variance. This type of watermark allows the detector to statistically check the presence or absence of the embedded watermark. In the second approach, a picture representing a company logo or other copyright information is embedded in the cover image. The detector actually reconstructs the watermark, and computes its visual quality using an appropriate measure. </div></div></span></div><br /><span style="font-weight:bold;"><br />VIDEO DEMO</span><br /><br /><object width="425" height="344"><param name="movie" value="http://www.youtube.com/v/2KFhtZb2oDI&hl=en&fs=1"></param><param name="allowFullScreen" value="true"></param><param name="allowscriptaccess" value="always"></param><embed src="http://www.youtube.com/v/2KFhtZb2oDI&hl=en&fs=1" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="425" height="344"></embed></object><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-16442199354387034922009-01-18T22:02:00.005+05:302009-05-17T20:31:03.076+05:30A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE<div style="text-align: justify;"><span style="font-weight: bold;">Introduction</span><br /><br />This project describes a novel architecture of Universal Asynchronous Receiver Transmitter (UART) based on Recursive Running Sum (RRS) filter. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The robust UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one third of required bit period. The intermediate data bit is decoded using magnitude comparator. A majority voter is used to decode actual data bit from three intermediate data bits.<br /><br />Universal Asynchronous Receiver Transmitter (UART) is used for asynchronous serial data communication between remote embedded systems. Standard UART cores three mid-bit samples to decode the serial data bit and the sampling rate is derived from external timer module. But if the physical channel is noisy then data bits get corrupted during transmission and it leads to wrong data decoding at receiver. To overcome the noise problem a digital low pass filter based architecture is proposed in this project.<br /><br />Recursive Running Sum (RRS) is simple low pass filter, it can be used to remove noise samples from data samples at receiver .Serial receive data signal is directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable and it decides baud rate. The robust UART core can be designed using Verilog HDL and can be implemented on Xilinx/ALTERA FPGA .<br /><br /></div><object width="320" height="266" class="BLOG_video_class" id="BLOG_video-8674f746d6365e13" classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000" codebase="http://download.macromedia.com/pub/shockwave/cabs/flash/swflash.cab#version=6,0,40,0"><param name="movie" value="//www.youtube.com/get_player"><param name="bgcolor" value="#FFFFFF"><param name="allowfullscreen" value="true"><param name="flashvars" value="flvurl=http://redirector.googlevideo.com/videoplayback?id%3D8674f746d6365e13%26itag%3D5%26source%3Dblogger%26app%3Dblogger%26cmo%3Dsensitive_content%3Dyes%26ip%3D0.0.0.0%26ipbits%3D0%26expire%3D1457196700%26sparams%3Dip,ipbits,expire,id,itag,source%26signature%3D563578D096462F44D6CBCB3CCE8A538E16398CC5.B0CA9EBEC1A7A26928F6C36A7AD591940C523F90%26key%3Dck2&iurl=http://video.google.com/ThumbnailServer2?app%3Dblogger%26contentid%3D8674f746d6365e13%26offsetms%3D5000%26itag%3Dw160%26sigh%3DLEpfZwvmi3tcX8UsS5aLXtJL4XA&autoplay=0&ps=blogger"><embed src="//www.youtube.com/get_player" type="application/x-shockwave-flash" width="320" height="266" bgcolor="#FFFFFF" flashvars="flvurl=http://redirector.googlevideo.com/videoplayback?id%3D8674f746d6365e13%26itag%3D5%26source%3Dblogger%26app%3Dblogger%26cmo%3Dsensitive_content%3Dyes%26ip%3D0.0.0.0%26ipbits%3D0%26expire%3D1457196700%26sparams%3Dip,ipbits,expire,id,itag,source%26signature%3D563578D096462F44D6CBCB3CCE8A538E16398CC5.B0CA9EBEC1A7A26928F6C36A7AD591940C523F90%26key%3Dck2&iurl=http://video.google.com/ThumbnailServer2?app%3Dblogger%26contentid%3D8674f746d6365e13%26offsetms%3D5000%26itag%3Dw160%26sigh%3DLEpfZwvmi3tcX8UsS5aLXtJL4XA&autoplay=0&ps=blogger" allowFullScreen="true" /></object><br /><br />To Download this Video,<br /><a href="http://picasaweb.google.com/verilog.course/UART_RRSF#5336769241101327394">http://picasaweb.google.com/verilog.course/UART_RRSF#5336769241101327394</a><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com1tag:blogger.com,1999:blog-1828350959784409126.post-10031623379547300792009-01-03T10:32:00.000+05:302009-02-06T15:43:09.935+05:30SIMULATION MODEL OF INVISIBLE ROBUST WATERMARKING USING VLSI/MATLAB<div style="text-align: justify;"><span style="font-weight: bold;font-family:georgia;" >INTRODUCTION </span><br /><br /><span style="font-family:georgia;">Owing to the usage of Internet, concerns about protecting and enforcing intellectual property (IP) rights of the</span> <span style="font-family:georgia;">digital content are mounting. Unauthorized replication and manipulation of digital content is relatively easy and can</span> <span style="font-family:georgia;">be achieved with inexpensive tools. Digital rights management (DRM) systems address issues related to</span> <span style="font-family:georgia;">ownership rights of digital content. Various aspects of content management – namely, content identification, storage,</span><span style="font-family:georgia;">representation, and distribution – and IP rights management are highlighted in DRM.<br /><br />Although unauthorized access </span><span style="font-family:georgia;">of digital content is being prevented by implementing encryption technologies, these approaches do not prevent an</span> <span style="font-family:georgia;">authorized user from illegally replicating the decrypted content. igital watermarking is one of the key technologies</span> <span style="font-family:georgia;">that can be used in DRM systems for establishing ownership rights, tracking usage, ensuring authorized access,</span><span style="font-family:georgia;">preventing illegal replication, and facilitating content authentication. Therefore, a two-layer protection mechanism</span> <span style="font-family:georgia;">utilizing both watermarking and encryption is needed to build effective DRM systems that can address IP rights and </span><span style="font-family:georgia;">copyright issues . </span><br /><br /><br /><span style="font-family:georgia;">In this project, the invisible watermarking aspect of DRM. Digital watermarking is the process of</span><br /><span style="font-family:georgia;">embedding data, called a watermark, into a multimedia object such that the watermark can be detected whenever</span> <span style="font-family:georgia;">needed for DRM. The object may be an image, audio, video, text, or graphics. However, in this project</span><span style="font-family:georgia;">“image” is the primary multimedia object, but similar work can be undertaken for other multimedia objects. In</span> <span style="font-family:georgia;">general, any watermarking algorithm consists of three parts: the watermark, the encoder (insertion algorithm),</span> <span style="font-family:georgia;">and the decoder and comparator (verification or extraction or detection algorithm). An entity, called the</span> <span style="font-family:georgia;">watermark key, which is unique and exhibits a one-to-one correspondence with every watermark, is also used during</span> <span style="font-family:georgia;">the process of embedding and detecting the watermark.<br /><br />The key is private and known only to authorized parties,</span><span style="font-family:georgia;">eliminating the possibility of illegal usage of digital content.</span><span style="font-family:georgia;">Watermarks and watermarking techniques can be divided into different categories in various ways</span><span style="font-family:georgia;">.Watermarks can be embedded in various domains, including the spatial and the frequency domains. The</span> <span style="font-family:georgia;"></span><span style="font-family:georgia;"></span><span style="font-family:georgia;">various transformations that have been used extensively as alternatives to the spatial domain are the discrete cosine</span> <span style="font-family:georgia;">transform (DCT), the Fourier transform (FT), and the wavelet transform (WT). Frequency-based methods have</span> <span style="font-family:georgia;">several advantages over spatial domain methods.For example, DCT domain techniques are more</span> <span style="font-family:georgia;">robust to attacks, and the perceptible quality of DCT domain watermarked images is better. On the other hand,</span> <span style="font-family:georgia;">spatial domain watermarking algorithms have less computational overhead than frequency domain algorithms. Spatial</span> <span style="font-family:georgia;">domain watermarking algorithms can also be faster in terms of computational time and hence are more suitable</span> <span style="font-family:georgia;">for real-time applications. Thus, we have focused on spatial domain watermarking because our ultimate goal is to</span> <span style="font-family:georgia;">develop VLSI architectures and chips such that real-time watermarking in the framework of electronic components</span> <span style="font-family:georgia;">would be possible.</span><span style="font-family:georgia;">Digital watermarks can be divided into visible and invisible types, based on human perception</span><span style="font-family:georgia;">. </span><span style="font-family:georgia;"><br /><br />A visible watermark is a secondary translucent image overlaid onto the primary image. An invisible</span> <span style="font-family:georgia;">watermark, on the other hand, is completely imperceptible. An invisible robust watermark is embedded in such a way</span> <span style="font-family:georgia;">that alterations made to the pixel value are not noticeable and can be recovered only with the appropriate decoding</span> <span style="font-family:georgia;">mechanism. An invisible fragile watermark is embedded in such a way that any manipulation or modification</span> <span style="font-family:georgia;">of the image would alter the watermark. </span><br /><br /><span style="font-weight: bold;font-family:georgia;" >INVISIBLE WATERMARKING ALGORITHMS</span><br /><br /><span style="font-family:georgia;">Invisible robust image watermarking algorithm and an invisible fragile image</span> <span style="font-family:georgia;">watermarking algorithm whose VLSI architecture and chips are described in subsequent sections. The algorithms</span> <span style="font-family:georgia;">selected are simple and effective and, with modifications, can result in high-performance hardware that can perform</span> <span style="font-family:georgia;">watermarking in real time. We discuss the insertion and detection methods in brief, with the modifications necessary</span> <span style="font-family:georgia;">to facilitate hardware implementation. </span><span style="font-family:georgia;"></span></div><br /><br /><span style="font-weight:bold;">VIDEO DEMO</span><br /><object width="340" height="285"><param name="movie" value="http://www.youtube.com/v/ugtBhw08d2I&hl=en&fs=1&rel=0&border=1"></param><param name="allowFullScreen" value="true"></param><param name="allowscriptaccess" value="always"></param><embed src="http://www.youtube.com/v/ugtBhw08d2I&hl=en&fs=1&rel=0&border=1" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="340" height="285"></embed></object><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-24449129092350382882008-12-03T22:42:00.003+05:302009-02-06T15:39:05.156+05:30An FPGA-based Architecture for Real Time Image Feature Extraction<div style="text-align: justify;"><span style="font-weight: bold;">Introduction</span><br /><br />Realtime image pattern recognition is a challenging task which involves image processing, feature extraction and pattern classification. It applies to a wide range of applications including multimedia, military and medical ones. Its high computational requirements force systems to use very expensive clusters, custom VLSI designs or even both. These approaches suffer from various disadvantages, such as high cost and long development times.<br /><br />Recent advances in fabrication technology allow the manufacturing of high density and high performance Field Programmable Gate Arrays (FPGAs) capable of performing many complex computations in parallel while hosted by conventional computer hardware. A variety of architecture designs capable of supporting realtime pattern recognition have been proposed in the recent literature, such as implementations of algorithms for image and video processing, classification and image feature extraction algorithms .<br /><br />Although texture plays a significant role in image analysis and pattern recognition only a few architectures implement on-board textural feature extraction. Most prominent approaches include the extraction of Gabor wavelet features for face/object recognition and the computation of mean and contrast Gray Level Cooccurrence Matrix (GLCM) features. In the second case the two features are approximated without computing GLCMs.In this project a novel FPGA-based architecture for realtime GLCM texture analysis.<br /><br />The combines both software and hardware to raster scan input images with sliding windows and produce 16-dimensional feature vectors consisting of four GLCM features calculated for four directions.</div><br /><span style="font-weight:bold;">VIDEO DEMO</span><br /><object width="340" height="285"><param name="movie" value="http://www.youtube.com/v/DQdNUQYGfrI&hl=en&fs=1&rel=0&border=1"></param><param name="allowFullScreen" value="true"></param><param name="allowscriptaccess" value="always"></param><embed src="http://www.youtube.com/v/DQdNUQYGfrI&hl=en&fs=1&rel=0&border=1" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="340" height="285"></embed></object><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-31857051029893155292009-01-26T14:06:00.002+05:302009-01-26T14:12:55.328+05:30IMPLEMENTATION OF RIJNDAEL S-BOX USING COMBINATIONAL LOGIC<div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">Introduction</span></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;"><br /></span></div><div style="text-align: justify;">This Project presents a combinational logic based Rijndael S-Box implementation for the SubByte transformation in the Advanced Encryption Standard (AES) algorithm for Field Programmable Gate Arrays (FPGAs). Recent publications on AES implementation have shown that the combinational logic based S-Box is proven for its small area occupancy and high throughput, given the fact that pipelining can be applied to this S-Box implementation as compared to the typical ROM based lookup table implementation which access time is fixed and unbreakable. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">The Project deals with a brief introduction to the Advanced Encryption Standard, the SubByte and InvSubByte transformation, and finally a short discussion on the previous h ardware implementations of the SubByte/InvSubByte transformation.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">The Advanced Encryption Standard</span> </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">The AES algorithm has a fixed block size of 128 bits and a key length of 128, 192 or 256 bits. It generates its key from an input key using the Key Expansion function. The AES operates on a 4x4 array of bytes which is called a state. The state undergoes 4 transformations which are namely the AddRoundKey, SubByte, ShiftRow and MixColumn transformation.The AddRoundKey transformation involves a bitwise XOR operation between the state array and the resulting Round Key that is output from the Key Expansion function. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">SubByte transformation is a highly non-linear byte substitution where each byte in the state array is replaced with another from a lookup table called an S-Box. ShiftRow transformation is done by cyclically shifting the rows in the array with different offsets. Finally, MixColumn transformation is a column mixing operation, where the bytes in the new column are a function of the 4 bytes of a column in the state array.Of all the transformation above, the SubByte transformation is the most computationally heavy.The SubByte and InvSubByte Transformation The SubByte transformation is computed by taking the multiplicative inverse in GF(28) followed by an affine transformation. For its reverse, the InvSubByte transformation, the inverse affine transformation is applied first prior to computing the multiplicative inverse.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">The steps involved for both transformation is shown below. </div><div style="text-align: justify;">SubByte: Multiplicative Inversion in GF(28) ->Affine Transformation </div><div style="text-align: justify;">InvSubByte:Inverse Affine Transformation ->Multiplicative Inversion in GF(2*8)<br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-80003028871767889892009-01-19T21:55:00.003+05:302009-01-19T22:05:21.388+05:30A VHDL/VERILOG MODEL OF A IEEE1451.2 SMART SENSOR:CHARACTERIZATION AND APPLICATIONS<div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">INTRODUCTION</span></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;"><br /></span></div><div style="text-align: justify;">New sensors are required to be small, cheap, and smart. This project deals with intelligent sensors embedded in a single chip: a Verilog/VHDL model of an IEEE1451.2 Smart Sensor is proposed to obtain a portable STIM block suitable for customizable compact solutions and allowing low-cost, large-scale production. In order to evaluate performances of the proposed model, working prototypes have been built and some tests have been carried out in a real case (chemical detection sensors). The proposed Verilog/VHDL model has been compared with traditional, software-based, microcontroller solutions showing that a timing performance improvement greater than 50% can be obtained. Finally, to exemplify effectiveness of a portable VHDL model, a single-chip sensor with USB interface and integrated IEEE1451 structures has been realized and experimentally characterized. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">In this projectaper, IEEE 1451 Standards are considered. Nowadays, some vendors supply smart sensors adherent to IEEE1451.2, the standard part that describes Smart Transducer Interface Module (STIM), Transducer Electronic DataSheet (TEDS), and Transducer Independent Interface (TII). Generally, these sensors have a microprocessor-centered architecture, where the CPU is devoted both to handle sensing element signal and to support IEEE1451.2 structure .However, it is said that few commercial products (e.g., Telemonitor TMI931A) are currently supporting IEEE1451.2 because of its relatively high cost; actually vendors prefer IEEE1451.4 , a simpler and cheaper standard solution. It is suitable for analog transducers (e.g., ENDEVCO i-TEDS accelerometers), since it defines only TEDS and requires a small number of additional components. In order to obtain a fast and more compact system, the systemon-chip (SoC) approach can be pursued; C (microcontroller), conditioning electronics, and even sensors can be integrated in one chip, reducing overall cost and simplifying assembly procedures . </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;"><div style="text-align: justify;"><span class="Apple-tab-span" style="white-space:pre"> </span><br /></div></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-33608320759291390452008-01-13T20:47:00.000+05:302009-01-13T20:49:34.420+05:30VLSI PROJECT LIST(Reference)<div><ol><li style="text-align: justify;">A NOVEL CARRY-LOOK AHEAD APPROACH TO AN UNIFIED BCD AND BINARY ADDER/SUBTRACTOR <br /></li><li style="text-align: justify;">SPECULATIVE CARRY GENERATION WITH PREFIX ADDER USING VERILOG<br /></li><li style="text-align: justify;">HIGHER RADIX AND REDUNDANCY FACTOR FOR FLOATING POINT SRT DIVISION USING VERILOG<br /></li><li style="text-align: justify;">AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL<br /></li><li style="text-align: justify;">REGISTER FOR PHASE DIFFERENCE BASED LOGIC <br /></li><li style="text-align: justify;">DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE ADDER WITH NEW REVERSABLE GATE <br /></li><li style="text-align: justify;">NOVEL BCD ADDERS AND THEIR REVERSIBLE LOGIC IMPLEMENTATION FOR IEEE 754R FORMAT<br /></li><li style="text-align: justify;">HIGH SPEED RECURSION ARCHITECTURE FOR MAP- BASED TURBO DECODERS <br /></li><li style="text-align: justify;">CONCURRENT ERROR DETECTION IN REED SOLOMON ENCODERS AND DECODERS<br /></li><li style="text-align: justify;">LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENT-ADDRESSABLE MEMORY USING VERILOG<br /></li><li style="text-align: justify;">L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL<br /></li><li style="text-align: justify;">LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION LOGIC FOR HIGH-SPEED FLOATING POINT UNITS<br /></li><li style="text-align: justify;">FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER <br /></li><li style="text-align: justify;">LOW POWER MULTIPLIER WITH SUPERIOUS POWER SUPRESSION TECHNIQUE<br /></li><li style="text-align: justify;">SHIFT INVERT CODING FOR LOW POWER VLSI<br /></li><li style="text-align: justify;">LOW POWER HARDWARE ARCHITECTURE FOR VBSME USING PIXEL TRUNCATION USING VHDL <br /></li><li style="text-align: justify;">A MODELING OF A DYNAMICALLY RECONFIGURABLE PROCESSOR USING VHDL <br /></li><li style="text-align: justify;">A PROCESSOR IN MEMORY ARCHITECTURE FOR MULTIMEDIA COMPRESSION <br /></li><li style="text-align: justify;">A VLSI PROGRESSIVE CODING FOR WAVELET BASED IMAGE COMPRESSION <br /></li><li style="text-align: justify;">SHIFT REGISTER BASED DATA TRANSPOSITION FOR COST EFFECTIVE DISCRETE COSINE TRANSFORM <br /></li><li style="text-align: justify;">FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM USING VHDL<br /></li><li style="text-align: justify;">DESIGN AND IMPLEMENTATION OF AES USING VHDL <br /></li><li style="text-align: justify;">EFFECTIVE USES OF FPGAS FOR BRUTE-FORCE ATTACK ON RC4 CIPHERS<br /></li><li style="text-align: justify;">A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE<br /></li><li style="text-align: justify;">COMPACT HARDWAE DESIGN OF WHIRLPOOL HASHING CORE <br /></li><li style="text-align: justify;">REAL TIME ADAPTIVE SPEECH WATERMARKING SCHEME FOR MOBILE APPLICATIONS <br /></li><li style="text-align: justify;">A LIGHTWEIGHT ENCRYPTION METHOD SUITABLE FOR COPYRIGHT PROTECTION <br /></li></ol></div><div style="text-align: justify;"><br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-69125865156532160332008-12-02T19:13:00.005+05:302009-01-12T10:29:34.338+05:30VLSI PROJECT LIST<span style="font-weight: bold;">VLSI</span><br /><br /><span style="font-weight: bold;">IEEE PROJECTS</span><br /><br />1. DES Algorithm.<br />2. AES Algorithm.<br />3. Viterbi Algorithm-Decoder.<br />4. Viterbi Algorithm-Encoder.<br />5. DDRR Algorithm.<br />6. Deficit Round Robin Algorithm.<br />7. FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm.<br />8. Dynamic Round Robin Algorithm.<br />9. Watermarking in a Secure Still Digital Camera Design.<br />10. Implementation of Lossless Data Compression and Decompression using (Parallel Dictionary Lempel Ziv Welch) PDLZW Algorithm.<br />11. 8/16/32 Point Fast Fourier Transform Algorithm.<br />12. Booths Algorithm.<br />13. VLSI Implementation of High Speed Reed‐Solomon Decoder.<br />14. UART.<br />15. On the Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICs.<br />16. VLSI implementation of Cascaded-Integrator-Comb Filter.<br />17. VLSI implementation of Wave-Digital-Filters.<br />18. VLSI implementation of Notch filters.<br />19. VLSI implementation of FIR filters.<br />20. Method for VLSI implementation of fractional sample rate converter (FSRC) and corresponding converter architecture.<br />21. Area optimized architecture and VLSI implementation of RC5 ALGORITHM.<br />22. VLSI implementation of canonical Huffman decoder.<br />23. Area optimized architecture and VLSI implementation of RC5 Decryption ALGORITHM.<br />24. VLSI implementation of canonical Huffman encoder.<br />25. VLSI implementation of canonical Huffman algorithm.<br />26. VLSI implementation of Stegnography.<br />27. Area optimized architecture and VLSI implementation of RC5 Encryption ALGORITHM.<br />28. 16 Bit fixed point DSP Processor.<br />29. VLSI Implementation of Address Generation Coprocessor.<br />30. Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm.<br />31. Implementation of LZW Data Compression Algorithm.<br />32. A Low Power Multiplier with SPST.<br />33. A Low Power VLSI Implementation for JPEG2000 Codec.<br />34. A Verilog Implementation of Built In Self Test of UART.<br />35. Fuzzy based PID Controller using VHDL for Transportation Application.<br />36. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication.<br />37. Power conscious test synthesis and scheduling.<br />38. The CSI Multimedia Architecture.<br />39. An Area-Efficient Universal Cryptography Processor for Smart Cards.<br />40. Block-Based Multi period Dynamic Memory Design for Low Data-Retention Power.<br />41. Cost effective SHA hardware accelerators.<br />42. Scalable multi giga bit pattern matching for packet inspection.<br />43. An FPGA-based Architecture for Real Time Image Feature Extraction.<br />44. Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications.<br />45. An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVClH.264 Transform Coding Design.<br />46. Synchronization in Software Radios - Carrier and Timing Recovery Using FPGAs.<br />47. Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor.<br />48. High-Speed Booth Encoded Parallel Multiplier Design.<br />49. Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications.<br />50. Implementation of IEEE 802.11a WLAN Baseband Processor.<br />51. An Efficient Spurious Power Suppression Technique (SPST) and its Applications on MPEG-4 AVClH.264 Transform Coding Design.<br /><br /><span style="font-weight: bold;">VLSI WITH MATLAB</span><br /><br />1. DCT Modified Algorithms Implemented in FPGA Chips for Real-Time Image Compression.<br />2. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication.<br />3. DCT and IDCT Implementations on Different FPGA Technologies.<br />4. Implementation of Watermarking Algorithm.<br />5. Secure transmitting and receiving text data in communication systems.<br />6. VLSI architecture for Cryptography algorithm.<br />7. Image filtering using VLSI.<br />8. Implementation of Edge detection method.<br />9. Robust Image Watermarking Based on Multiband Wavelets and Empirical Mode Decomposition.<br />10. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design.<br /><br /><span style="font-weight: bold;">COMMUNICATION BASED PROJECTS</span><br /><br />1. Asynchronous Transmitter.<br />2. Asynchronous Receiver.<br />3. Mini UART.<br />4. Micro UART.<br />5. RS-232 Transmitter/Receiver.<br />6. GPS-GSM Mobile Navigator.<br />7. Simple Asynchronous Serial controller.<br />8. USART.<br />9. Universal Serial Bus Device Controller.<br />10. Universal Serial Bus 1.1 Receiver.<br />11. Universal Serial Bus 1.1 Transmitter.<br />12. GPS-GSM based Home Automation System.<br /><br /><span style="font-weight: bold;">PROCESSOR BASED PROJECTS</span><br /><br />1. Low Power RISC Processor.<br />2. CISC Processor.<br />3. Smart Processor.<br />4. Robotic Applications for Microcontroller.<br />5. 16 bit Processor.<br /><br /><span style="font-weight: bold;">STORAGE BASED PROJECTS</span><br /><br />1. Two wire Serial EEPROM.<br />2. I2C.<br />3. Process Controller.<br />4. Design of Memory with counter as address register.<br />6. Temperature and Humidity Controller.<br />7. USB Embedded Clocking.<br />8. Design of Asynchronous FIFO.<br />9. Design of Synchronous FIFO.<br />10. ALU.<br />11. I2S.<br />12. Multichannel I2S.<br /><br /><span style="font-weight: bold;">GENERAL PROJECTS</span><br /><br />1. Huffman Encoder/Decoder<br />2. Programmable 16-Tap FIR Filter.<br />3. 2-D Convolution Engine.<br />4. VGA/LCD Controller.<br />5. JTAG TAP controller.<br />6. Booth Multiplier.<br />7. Pipeline Implementation of baseline JPEG Encoder.<br />8. Dual Loop DLL.<br />9. Design of Arbiter.<br />10. Design of Multiplier using spurious power suppression technique.<br />11. Design of encoder.<br />12. Design of decoder.<br />13. Design and Implementation of Median filter.<br />14. Cyclic Redundancy Check Error Check.<br />15. Design of 8bit to 10 bit Encoding Techniques.<br />16. LCRC Error Check.<br />17. ECRC Error Check.<br />18. Auto Tracking & Safety System.<br />19. Design of Low Power FIR Filter.<br />20. Design of Music Box.<br />21. Design of Pattern Detector.<br />22. Design of One hot state machine for FPGA design.<br /><br /><span style="font-weight: bold;">BUS PROTOCOLS PROJECTS</span><br /><br /><span style="font-weight: bold;">AMBA </span><br /><br />1. AMBA AHB full.<br />2. AHB Master.<br />3. AHB Slave.<br />4. AMBA AHB to PVCI Bridge.<br /><br /><span style="font-weight: bold;">PCI EXPRESS </span><br /><br />1. PCI Express full<br />2. Data Link Layer Receiver Block.<br />3. Physical Layer Receiver Block.<br />4. Transaction Layer Receiver Block.<br />5. Data Link Layer Sequence Number Check.<br />6. Data Link Layer LCRC Check.<br />7. Data Link Layer DCRC Check.<br />8. Data link Layer Align Block.<br />9. Flow Control in PCI Express.<br />10. Power Management in PCI Express.<br />11. Data Link Layer Transmit Block.<br />12. Physical Layer Transmit Block.<br />13. Transaction Layer Transmit Block.<br />14. Data Link Layer Control Block.<br />15. Physical Layer Control Block.<br />16. Transaction Layer Control Block.<br />17. PCI Express End Point.<br /><br /><span style="font-weight: bold;">USB</span><br /><br />1. USB 2.0.<br />2. USB 1.0.<br />3. USB OTG.<br />4. USB OTG MAC.<br /><br /><span style="font-weight: bold;">PVCI</span><br /><br />1. PVCI Full.<br />2. PVCI Master.<br />3. PVCI Slave.<br /><br /><span style="font-weight: bold;">SOC PROJECTS</span><br /><br />1. CAN Controller.<br />2. Wishbone Controller.<br /><br />Send your new ideas with related document to <span style="font-weight: bold;">verilog.course@gmail.com. Or Call +91 98942 20795</span><br /><br /><span style="font-weight: bold;">The above listed topics are to provide you some ideas.</span><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-23360225830150848892009-01-01T11:09:00.003+05:302009-01-01T11:17:58.248+05:30A REAL-TIME IMPLEMENTATION OF CHAOTIC CONTOUR TRACING AND FILLING OF VIDEO OBJECTS ON RECONFIGURABLE HARDWARE<div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;">INTRODUCTION</span></div><div style="text-align: justify;"><span class="Apple-style-span" style="font-weight: bold;"><br /></span></div><div style="text-align: justify;">Contour tracing is a method that links connected neighborhood pixels in a binary edge frame, whereas contour filling fills the area inside a contour with a specific integer value, uniquely labeling each objects in an image. Contour tracing and filling are a fundamental element in many video and image processing applications such as video surveillance, medical image processing, computer vision and pattern recognition. Recently, solutions for robust contour tracing and filling methods have been considerably investigated using the state of the-art general purpose sequential processors.</div><div style="text-align: justify;"><br /></div><div style="text-align: justify;"> However, these software-based implementations are too slow to archive real-time performance due to the high computational and memory bandwidth inherently required in contour tracing and filling algorithms. As such, an efficient hardware acceleration is inevitable. Although traditional full custom Application Specific Integrated Circuits (ASICs) provide high performance with low power and area, they suffer from flexibility, longer development time and expensive engineering cost. </div><div style="text-align: justify;"><br /></div><div style="text-align: justify;">In contrast, emerging FPGAs with embedded multipliers, memory blocks and high pin counts, are increasingly employed on hardware platforms in many signal/video processing applications. In this project, a proposed real-time, scalable and compact FPGA-based architecture for contour analysis. We utilize the FPGA heterogeneous resources efficiently, and employ advanced design techniques such as heavy pipelining and data parallelism to achieve high throughput but minimizing area and power dissipation. <br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-83050681759877666232008-12-27T17:23:00.002+05:302008-12-27T17:32:02.120+05:30ROBUST IMAGE WATERMARKING BASED ON MULTIBAND WAVELETS AND EMPIRICAL MODE DECOMPOSITION<div style="text-align: justify;">INTRODUCTION<br /><br />With the rapid development of internet and wireless networks, multimedia security and digital rights management (DRM) are becoming increasingly important issues,.Te watermarking system has been viewed as a possible solution to control unauthorized duplication and redistribution of those multimedia data. Robustness, perceptually invisibility,and security are the basic requirements for a robust watermarking system. Seeking new watermark embedding strategy to achieve performance is a very challenging problem. In this project, a proposed new blind image watermarking scheme, which is based on the multiband wavelet transform and the empirical mode decomposition.<br /><br />The watermark bits can be embedded either in the spatial domain or in the transform domain, while the latter watermark embedding strategy has been demonstrated to be more robust against most of attacks. We take that latter watermarking embedding strategy in our image watermark embedding scheme, particularly we embed watermark bits indirectly in the multiband wavelet domain with the dilation factor M>2 . For M=2 , there are lots of watermarking schemes available. For instance, Prayoth et al. introduced a semi-blind watermarking scheme based on the two-band multiwavelet transform.Hsieh et al proposed a nonblind watermarking scheme based on the two-band wavelet transform and the qualified significant wavelet tree (QSWT), which is robust to JPEG compression, image cropping, median filter etc., Lahouari et al suggested a watermarking algorithm based on the balanced two-band multiwavelet transform and the well-established perceptual model, which is adaptive and highly robust.<br /><br />Ng et al put forward a maximum-likelihood detection scheme that is based on modelling the distribution of the image DWT coefficients using a Laplacian probability distribution function. In Bao et al. proposed a watermarking scheme by using a quantization-index-modulation (QIM) process via wavelet domain singular value decomposition (SVD). That scheme is robust against JPEG compression but extremely sensitive to filtering and random noising.<br /><br />In this project, we use the multiband wavelet domain, instead of the two-band wavelet domain, to embed the watermark bits for the reason that the multiband wavelet domain provides more capacity for watermarking and more flexible tiling of the scale-space plane. Particularly, applying the MWT with the dilation factor an image is decomposed into subimages with narrower frequency bandwidth in different scales and directions. The subimages thus generated with middle frequency are favorable blocks to embed watermark bits in our watermark embedding strategy due to the robustness against JPEG compression and various noise attacks.<br /><br />For the robustness of an image watermarking system, the watermark bits are usually embedded in the perceptually significant components, mostly the low or middle frequency components of the image . he EMD, first proposed in and later demonstrated to be very useful in many areas , provides a self-adaptive decomposition of a signal, and the mean trend, the coarsest component, of the signal is highly robust under noise attack and JPEG compression. So, we select the mean trend of each subimage in the multiband wavelet domain, instead of the subimage itself, to embed the watermark bits. Our experimental results show that the watermarking based on the MWT and EMD is robust against JPEG compression, Gaussian noise, Salt and Pepper noise, median filtering and ConvFilter (Gaussian filtering and sharpening) attacks. </div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0tag:blogger.com,1999:blog-1828350959784409126.post-2880259227162802462008-12-24T23:48:00.002+05:302008-12-25T00:00:14.562+05:30HIGH-SPEED BOOTH ENCODED PARALLEL MULTIPLIER DESIGN<div style="text-align: justify;"><span style="font-weight: bold;">INTRODUCTION</span><br /><br />IN various computing and signal processing applications, parallel multiplier has been a basic building block for many algorithms. Many high performance algorithms and architectures have been proposed to accelerate multiplication. Multiplication can be divided into three steps:<br />generating partial products,<br /><br />summing up all partial products until only two rows remain,<br />and adding the remaining two rows of partial products by using a carry propagation adder.<br /><br />In the first step, two methods are commonly used to generate partial products. The first method generates partialproduct directly by using a 2-input AND gate. The second one uses radix-4 modified Booth encoding (MBE) to generate partial products. Radix-4 MBE has been widely used in parallel multipliers to reduce the number of partial products by a factor of two. In the speed performance of using radix-4 MBE was denied. However, it is found herein that these results depend on the implementation of MBE scheme.<br /><br />After generating partial products, a partial product reduction tree (PPRT) is used to sum up all the partial products efficiently. The Wallace tree and Carry-save tree were developed to solve this problem. Both approaches employ 3:2 counter, i.e., full adder, as their basic element. Generally, a counter compresses (n-1) rows of partial products into log2 (n)rows of partial products. However, the delay of an n ÿ 1 : log2 n(n)counter is still proportional to log2 (n) 1 times of a full adder (FA) as the inputs are assumed to arrive simultaneously. Therefore, using larger counters to build PPRT is not beneficial. The introduction of 4:2 compressor was a departure from the counter-based scheme. As the delay paths are well balanced, the latency for a 4:2 compressor is only three XOR delays, rather than two full adder delays. Note that the difference between the compressor and the traditional balanced delay tree is that the compressor considers the fast path and the slow path of a full adder. To further speed up, a search algorithm, Three-Dimensional- reduction-Method (TDM) , was proposed.<br /><br />The TDM algorithm finds optimal PPRT by carefully modeling the delay paths of a counter and constructing n:2 column compressor according to inputs arrival time. Owing to the effectiveness of the column compressor, the PPRT constructed by using TDM algorithm outperforms the conventional designs. However, few studies have been done on using TDM with MBE. This paper examines the performance of parallel multiplier constructed with TDM and MBE. According to our results, such a design can be faster and occupy a smaller area than a non-Booth design.To generate the product in 2's complement format, a fast carry-propagation adder is required to add the final two rows of partial products from the PPRT.<br /><br />The problem of designing a final adder is that the input signals do not arrive simultaneously, unlike the ordinary carry-propagation adder design that assumes all the inputs arrive simultaneously. Several techniques have been developed to eliminate or reduce the final adder delay. The Left-to-Right-Carry-Free algorithm proposed in requires n-level conversions to generate n-bit MSB products. It was improved in by reducing the levels required. However, this approach still cannot fully exploit the unequal delay profile because it applies to the MSB-part only. In a hybrid adder structure, which consists of ripple-carry adder, carry-skip adder, and conditional-sum adder blocks, was proposed. However, their empirical methodology is not general enough and requires many trials to determine the final adder partition boundary for different sizes of multiplier, thus increasing design effort. In this project, a propose design methodology for high-speed Booth encoded parallel multiplier.<br /></div><div class="blogger-post-footer">Click Here</div>.http://www.blogger.com/profile/12231586279374897112noreply@blogger.com0