VLSI IEEE PROJECT TOPICS

VLSI IEEE PROJECT TOPICS

· Area-Efficient Universal Cryptography Processor for Smart Cards

· The CSI Multimedia Architecture

· VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn -

· Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation

· A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications-

· Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application-

· Implementation of IEEE 802.11 a Wlan Baseband Processor

· A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture

· A Verilog Implementation of UART Design with Bist Capability

· A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance

· Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications

· A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)

· A Low-Power Multiplier With The Spurious Power Suppression Technique

· Design Of Reconfigurable Coprocessor for Communication Systems

· Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power

· A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems

· On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics

· Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications

· Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA

· Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

· An Fpga-Based Architecture for Real Time Image Feature Extraction

· Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm

· Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication

· Fpga Based Power Efficient Channelizer for Software Defined Radio

· FPGA Implementation(s) of a Scalable Encryption Algorithm.

· Simulation Based Edge Detection.

VISIT://www.verilogcourseteam.com/academic-solutions for more details

SIMULATION MODEL OF VISIBLE WATERMARKING FOR JPEG IMAGE (3 D) USING VLSI/MATLAB

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This project presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework.

Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. The watermarking object may be an image, audio, video, or text .Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection.

According to human perception, the digital watermarks can be divided into four categories:

1) visible;

2) invisible-robust;

3) invisible-fragile;

4) dual

A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark . In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. There are numerous software-based watermarking schemes available in literature. A vast research community involving experts from computer science, cryptography, signal processing, and communications, etc., are working together to develop watermarks that can withstand different possible forms of attacks, each one of which has its own applications and thus is equally important. There is a gap between the image capture and image transmission in thewaywatermarking is used presently. Once the images are acquired,watermarks are inserted in them offline, and then images are made available. The objective of this research work is to implement hardware-based watermarking schemes so as to bridge that gap. The watermark chip will be fitted in the devices that acquire the image and watermark the images in real time while capturing.

VIDEO DEMO

SIMULATION OF HARDWARE BASED EDGE DETECTION

INTRODUCTION:

Edge detection is a fundamental tool used in most image processing applications to obtain information from the frames before feature extraction and object segmentation. This process detects outlines of an object and boundaries between objects and the background in the image. Beyond that, Edge Detection refers to the process of identifying and locating sharp discontinuities in intensities in an image. The discontinuities are abrupt changes in pixels intensity which characterize boundaries of objects in a scene structure. This process significantly reduces the amount of date in the image, while preserving the most important structural feature of that image. Edge detection is considered to be the ideal algorithm for images that are corrupted with white noise. The Edge is characterized by its height, slope angle,and horizontal coordinate of the slope midpoint. An ideal Edge Detector should produce an edge indication localized to a single pixel located at the midpoint of the slope.There are many ways to perform Edge detection. However, the majority of different methods may be grouped into two categories, gradient and Laplacian. The basic Edge detection operator is a matrix area gradient operation that determines the level of variance between different pixels. The edge detection operator is calculated by forming a matrix centered on a pixel chosen as the centre of the matrix area. If the value of the matrix area is above a given threshold, then the middle pixel is classified as an edge. Examples of gradient based edge detectors are Roberts, Prewitt and Sobel operators. All the gradient –based algorithms have Kernel operators that calculate the strength of the slope in directions that are orthogonal to each other, generally horizontal and vertical.
The requirements that the algorithms must meet are:
a) Show the effectiveness and the noise resistance for remote sensing image.
b) Satisfying real time-constraints, and minimizing hardware resources in order to meet embedding requirements.
c) Significantly reducing the amount of date and filters out useless information.

Classically, Edge detection algorithms are implemented on software. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithm yield significant speedup in running times. Implementation image processing on reconfigurable hardware minimizes the time-to-market cost, enables rapid prototyping of complex algorithm and simplifies debugging and verification.

VIDEO DEMO

Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

INTRODUCTION

The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate:

1) parallelizing the scrambler function and

2) concatenating the FEC encoder, puncturing, and inter leaver functions.

Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.

802.11A DIGITAL BASEBAND TRANSMITTER

The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel.

Table 1 lists the mode-dependent parameters for the 802.11a standard.

The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol.