VLSI IEEE PROJECT TOPICS

VLSI IEEE PROJECTS 

• Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing-2002
• DCT-Based Image Watermarking Using Subsampling-2003
• Shift Invert Coding (SINV) for Low Power VLSI-2004
• Robust DWT-SVD Domain Image Watermarking: Embedding Data in All Frequencies-2004
• Digital Design of DS-CDMA Transmitter Using VHDL and FPGA-2005
• Design of Edge Detection Systems
• A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)-2005
• A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture-2006
• An FPGA-based Architecture for Real Time Image Feature Extraction-2004
• Image Compression with Different Types of Wavelets-2006

2007 Topics

• A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier Low-power and high-quality Cordic-based Loeffler DCT for signal processing
• Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
• A Low-Power Multiplier With the Spurious Power Suppression Technique
• FPGA Implementation(s) of a Scalable Encryption Algorithm
• VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application

2008 Topics

• Fuzzy based PID Controller using VHDL for Transportation Application Research on Fast Super-resolution Image Reconstruction Base on Image Sequence
• A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
• FPGA Implementation Of Usb Transceiver Macrocell Interface With USB2.0 Specifications
• Multiplier design based on ancient Indian Vedic Mathematics
• A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
• Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications
• Implementation of IEEE 802.11 a WLAN Baseband Processor

2009 Topics

• The CSI Multimedia Architecture
• Design and Implementation of Boundary-Scan Circuit for FPGA
• Hardware Algorithm for Variable Precision Multiplication on FPGA
• VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPT
• VLSI Implementation of an Edge-Oriented Image Scaling Processor
• FPGA-Based Face Detection System Using Haar Classifiers
• An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM-Convolutional Encoders
• Fast Scaling in the Residue Number System
• VLSI Architecture and Chip for Combined Invisible Robust Watermarking
• Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
• An Area-Efficient Universal Cryptography Processor for Smart Cards
• FPGA Based Power Efficient Channelizer for Software Defined Radio
• Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
• Lossless Compression using Efficient Encoding of Bitmasks
• 3D Discrete Wavelet Transform VLSI Architecture for Image Processing
• A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

2010 Topics

• Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
• A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
• A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
• FPGA Implementations of the Hummingbird Cryptographic Algorithm
• FPGA Implementation(s) of a Scalable Encryption Algorithm
• A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
• Contrast Enhancement of Color Images using Tunable Sigmoid Function
• Image Compression with Different Types of Wavelets
• Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms using Xilinx System Generator.
• Design and FPGA Implementation of Modular Multiplication methods using Cellular Automata
• Image Edge Detection Based on FPGA
• VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN
• Improvisation of Gabor Filter design using Verilog HDL
• Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
• A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
• VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for JPEG

2011 Topics

• An Efficient Implementation of Floating Point Multiplier
• High Speed and Low Space Complexity FPGA Based ECC Processor
• A blind digital watermarking algorithm based on wavelet transform
• A Distributed Canny Edge Detector And Its Implementation on FPGA
• Design and Simulation of UART Serial Communication Module Based on VHDL
• Design and VLSI implementation of high-performance face-detection engine for mobile applications
• Design and Implementation of Area-optimized AES based on FPGA
• Design of Low Power And High Speed Configurable Booth Multiplier
• Face detection and recognition method based on skin color and depth information
• High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
• A New Reversible Design of BCD Adder
• Digital Image Authentication from JPEG Headers
• Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
• Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
• A Very Fast and Low Power Carry Select Adder Circuit
• A_multichannel watermaking scheme based on DCT-DWT
• An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
• Design and Characterization of Parallel Prefix Adders using FPGAs
• FPGA based FFT Algorithm Implementation in WiMAX Communications System
• FPGA Design of AES Core Architecture for Portable Hard Disk
• FPGA Implementation of RS232 to Universal serial bus converter
• Image Encryption Based On AES Key Expansion
• Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
• An Efficient Architecture Design for VGA Monitor Controller
• Curve Fitting Algorithm FPGA implementation
• FPGA Implementation of AES Algorithm
• Design of Low Power Column Bypass Multiplier using FPGA
• Design of Serial Communication Interface Based on FPGA
• Design and Implementation of an FPGA-based Real-Time Face Recognition System
• VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders
• Low Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
• Design of Low Power And High Speed Configurable Booth Multiplier
• Design Enhancement Of combinational Neural Networks using HDL Based FPGA framework for Pattern Recognition
• Efficient VLSI Architecture for Discrete Wavelet Transform

2012 Topics

• Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits
• Design of Low Power High Speed VLSI Adders SubSystem
• Synthesis and Implementation of UART using VHDL Codes
• HICPA: A Hybrid Low Power Adder for High-Performance Processors
• Low-Power and Area-Efficient Carry Select Adder
• Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics
• Design and Implementation of a High Performance Multiplier using HDL
• DESIGN Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER
• Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
• FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers
• High Speed and Area Efficient Vedic Multiplier
• High speed Modified Booth Encoder multiplier for signed and unsigned numbers
• An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
• High Speed Signed Multiplier for Digital Signal Processing Applications
• Accumulator Based 3-Weight Pattern Generation
• Design of Low Power TPG Using LP-LFSR
• Viterbi-Based Efficient Test Data Compression
• A Feature-Based Robust Digital Image Watermarking Scheme
• Digital Image Watermarking Based on Super Resolution Image Reconstruction
• Hardware Implementation of a Digital Watermarking System for Video Authentication
• Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code
• Watermarking Scheme for Copyright Protection of 3d Animated Model
• Efficiency of BCH Codes in Digital Image Watermarking
• Image Magnification by Modifying DCT Coefficients
• A Real-time Face Detection And Recognition System
• VHDL Implementation of UART with Status Register
• Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC
• FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
• Pipelined Parallel FFT Architectures via Folding Transformation
• VHDL Design for Image Segmentation using Gabor filter for Disease Detection.
• An  Efficient Viterbi Decoder.
• Improved Architectures for a Fused Floating-Point Add-Subtract Unit
• Very Low Resolution Face Recognition Problem
• Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

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The above listed topics are just for reference. If you have any new Ideas/Papers send to us at info@verilogcourseteam.com or Call +91 98942 20795.

SIMULATION MODEL OF VISIBLE WATERMARKING FOR JPEG IMAGE (3 D) USING VLSI/MATLAB

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This project presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework.

Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. The watermarking object may be an image, audio, video, or text .Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection.

According to human perception, the digital watermarks can be divided into four categories:

1) visible;

2) invisible-robust;

3) invisible-fragile;

4) dual

A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark . In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. There are numerous software-based watermarking schemes available in literature. A vast research community involving experts from computer science, cryptography, signal processing, and communications, etc., are working together to develop watermarks that can withstand different possible forms of attacks, each one of which has its own applications and thus is equally important. There is a gap between the image capture and image transmission in thewaywatermarking is used presently. Once the images are acquired,watermarks are inserted in them offline, and then images are made available. The objective of this research work is to implement hardware-based watermarking schemes so as to bridge that gap. The watermark chip will be fitted in the devices that acquire the image and watermark the images in real time while capturing.

VIDEO DEMO

SIMULATION OF HARDWARE BASED EDGE DETECTION

INTRODUCTION:

Edge detection is a fundamental tool used in most image processing applications to obtain information from the frames before feature extraction and object segmentation. This process detects outlines of an object and boundaries between objects and the background in the image. Beyond that, Edge Detection refers to the process of identifying and locating sharp discontinuities in intensities in an image. The discontinuities are abrupt changes in pixels intensity which characterize boundaries of objects in a scene structure. This process significantly reduces the amount of date in the image, while preserving the most important structural feature of that image. Edge detection is considered to be the ideal algorithm for images that are corrupted with white noise. The Edge is characterized by its height, slope angle,and horizontal coordinate of the slope midpoint. An ideal Edge Detector should produce an edge indication localized to a single pixel located at the midpoint of the slope.There are many ways to perform Edge detection. However, the majority of different methods may be grouped into two categories, gradient and Laplacian. The basic Edge detection operator is a matrix area gradient operation that determines the level of variance between different pixels. The edge detection operator is calculated by forming a matrix centered on a pixel chosen as the centre of the matrix area. If the value of the matrix area is above a given threshold, then the middle pixel is classified as an edge. Examples of gradient based edge detectors are Roberts, Prewitt and Sobel operators. All the gradient –based algorithms have Kernel operators that calculate the strength of the slope in directions that are orthogonal to each other, generally horizontal and vertical.
The requirements that the algorithms must meet are:
a) Show the effectiveness and the noise resistance for remote sensing image.
b) Satisfying real time-constraints, and minimizing hardware resources in order to meet embedding requirements.
c) Significantly reducing the amount of date and filters out useless information.

Classically, Edge detection algorithms are implemented on software. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithm yield significant speedup in running times. Implementation image processing on reconfigurable hardware minimizes the time-to-market cost, enables rapid prototyping of complex algorithm and simplifies debugging and verification.

VIDEO DEMO

Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

INTRODUCTION

The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate:

1) parallelizing the scrambler function and

2) concatenating the FEC encoder, puncturing, and inter leaver functions.

Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.

802.11A DIGITAL BASEBAND TRANSMITTER

The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel.

Table 1 lists the mode-dependent parameters for the 802.11a standard.

The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol.