- A NOVEL CARRY-LOOK AHEAD APPROACH TO AN UNIFIED BCD AND BINARY ADDER/SUBTRACTOR
- SPECULATIVE CARRY GENERATION WITH PREFIX ADDER USING VERILOG
- HIGHER RADIX AND REDUNDANCY FACTOR FOR FLOATING POINT SRT DIVISION USING VERILOG
- AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL
- REGISTER FOR PHASE DIFFERENCE BASED LOGIC
- DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE ADDER WITH NEW REVERSABLE GATE
- NOVEL BCD ADDERS AND THEIR REVERSIBLE LOGIC IMPLEMENTATION FOR IEEE 754R FORMAT
- HIGH SPEED RECURSION ARCHITECTURE FOR MAP- BASED TURBO DECODERS
- CONCURRENT ERROR DETECTION IN REED SOLOMON ENCODERS AND DECODERS
- LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENT-ADDRESSABLE MEMORY USING VERILOG
- L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL
- LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION LOGIC FOR HIGH-SPEED FLOATING POINT UNITS
- FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER
- LOW POWER MULTIPLIER WITH SUPERIOUS POWER SUPRESSION TECHNIQUE
- SHIFT INVERT CODING FOR LOW POWER VLSI
- LOW POWER HARDWARE ARCHITECTURE FOR VBSME USING PIXEL TRUNCATION USING VHDL
- A MODELING OF A DYNAMICALLY RECONFIGURABLE PROCESSOR USING VHDL
- A PROCESSOR IN MEMORY ARCHITECTURE FOR MULTIMEDIA COMPRESSION
- A VLSI PROGRESSIVE CODING FOR WAVELET BASED IMAGE COMPRESSION
- SHIFT REGISTER BASED DATA TRANSPOSITION FOR COST EFFECTIVE DISCRETE COSINE TRANSFORM
- FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM USING VHDL
- DESIGN AND IMPLEMENTATION OF AES USING VHDL
- EFFECTIVE USES OF FPGAS FOR BRUTE-FORCE ATTACK ON RC4 CIPHERS
- A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE
- COMPACT HARDWAE DESIGN OF WHIRLPOOL HASHING CORE
- REAL TIME ADAPTIVE SPEECH WATERMARKING SCHEME FOR MOBILE APPLICATIONS
- A LIGHTWEIGHT ENCRYPTION METHOD SUITABLE FOR COPYRIGHT PROTECTION
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