Training - Modules

Online/Regular Training will be provided in the following modules. Students/Trainees can have hands-on operations with the software’s (Windows/Linux) from their location.
Module: 1 -Digital Systems 20Hours
· Boolean Algebra
· Combinational /Sequential Circuits
· K-Map Simplification
· Flip flop and Latches
· State Machines
· Counters and Shift Registers
· Case Studies
Module: 2 –Verilog HDL Programming 45Hours
· Introduction to HDL
· Verilog Modeling Concepts
· Verilog HDL Conventions
· Data Types in Verilog
· Gate Level Modeling
· Data flow Modeling
· Operators
· Continuous Assignments
· Behavioral Modeling
· Compiler Directives
· Writing Verilog Models
· Tasks and Functions
· Test benches-Basics
· Assignments
Module: 3 –Verification 30Hours
· Verification Methodology
· Bus Functional Modeling
· Test bench/Test Case
· Code Coverage Analysis-Introduction
· Regression Testing
Module: 4 –FPGA Synthesis 20Hours
· Working Process with Synthesis tool
· Setting Constraints
· Timing Analysis-Introduction
· Documentation
Module: 5- FPGA Implementation 20Hours
· Implementation Procedures
· Setting Target Device
· Device Programming using ALTERA/XILINX
Module: 6 –ASIC Synthesis 30Hours
· ASIC Synthesis-Materials
· Working Process with Synthesis tool
· Setting Technology-libraries
· Setting Constraints
· Introduction to Shell and TCL scripting
· Documentation
Module: 7- EDA Simulation Tools 30Hours
· Mentor Graphics- Modelsim/Questasim
· Synopsys - VCS
· Cadence - NC Verilog/Verilog XL
Module: 8- EDA Synthesis Tools 30Hours
· Xilinx - Xilinx ISE (FPGA)
· Mentor Graphics - Leonardo Spectrum (FPGA)
· Synopsys - Design Complier (ASIC)
Module: 9- Operating Systems 20Hours
· Red Hat Linux
· Windows
· Sun Solaris
Module: 10- Documentation Tools 20Hours
· Adobe-Frame Maker
· Microsoft Office
Module: 11 - Project Planning/Management-Ideas 30Hours
· Design Specifications Analysis
· Directory Structure
· RTL Design
· Test Plan
· Test Environment
· RTL-Coding Guidelines
· Documentation
Module: 12 – PG Diploma in VLSI 3-Months
· Digital System
· Verilog HDL-Programming
· Project Analysis-(ASIC/FPGA Prototype)
· Personality Development
· Interview Skills-FAQS
· Necessary Documentation (Soft Copy)
Module: 13 – Real Time- Industry Standard Project (depends on Project Selection)
· AMBA –AHB
· PCI EXPRESS
· USB
· UART
· DES Algorithm
· AES Algorithm
· Viterbi Algorithm
· DDRR Algorithm
· CORDIC Algorithm
· Watermarking in a Secure Still Digital Camera Design.
· 8 Point Fast Fourier Transform Algorithm
· Booths Algorithm
· Wave-Digital-Filters
· Notch filters
· FIR filters
· Canonical Huffman algorithm and MANY MORE *Condition Apply
Mock Call -Interview
Send your resume, our team member will conduct telephonic interview with reference to your resume to give confidence while attending interviews. Premium charges apply.
· Interview time will be 30-60 Minutes. Question based on your resume/Verilog and Digital.
*Support will be provided as soon as possible depends on the availability of engineers. Please bear with us.
Note: Verilog Course Team is not a Institute.
Online/Regular Training will be provided by engineers working in respective domain.
Online Training will be provided using Net meeting / VNC Server.
For Module - 3,4,5,6,7,8,11,13 should have prior knowledge in Verilog HDL.
Time duration mentioned is approximately.