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Design of Reconfigurable Coprocessor for Communication Systems


The recent growth of communication services has resulted in a number of competing and incompatible standards. These standards include xDSL (Digital Subscriber Line) , WLAN (Wireless Local Area Network), DAB (Digital Audio Broadcast), DVB (Digital Video Broadcast), IMT-2000 (International Mobile Telecommunications-2000), etc. Each function performs similar operations in various standards.

However, it has different characteristics according to the standards. Hence, a flexible processor-based solution is more attractive than an ASIC solution. SDR (Software Defined Radio) is a flexible communication system that supports multi-mode and multi-band using programmable processors.However, recent development of programmable and reconfigurable structures based on FPGA or DSP cannot satisfy the standard requirement in efficiency and performance.

Thus, next generation communication processors will be high performance reconfigurable processors based on flexible structures, such as RP (Reconfigurable Processor), ASP (Application Specific Processor), ASIP (Application Specific Instruction Processor), etc. This project proposes a reconfigurable coprocessor for next generation communication systems. To verify the architecture, the proposed architecture to be modeled by Verilog and evaluated performance comparisons.


Hardware structures for next generation communication systems require flexibility, high performance and low power. However, these properties conflict each other and limit the hardware development. Thus, existing design methods and hardware structures cannot satisfy all of the properties. In this paper, we analyze various communication standards and propose the high performance reconfigurable communication coprocessor.

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