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VLSI IEEE 2018 Projects at Chennai

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A Low-Power Multiplier With the Spurious Power Suppression Technique

RS encoder has been proposed. The problems related to the presence of undetected faults in parity check-based schemes has been faced by imposing some constrains in the logical net-list implementation for the constant multiplier. Evaluations of area and delay overhead for the self-checking RS encoder has been provided. For the self-checking RS decoder two main properties of the fault free decoder have been identified and used to detect faults inside the decoder. The proposed method can be used for a wide range of algorithm implementing the decoder function. Some concurrent error detection schemes have been explained in the paper and some evaluations of area overhead has been provided. Our method is nonintrusive, i.e., the decoder architecture is not modified. This fact enables the use of the reusability concept, for the design of very complex digital systems.

This Project provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The SPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction.

The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. 

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