INTRODUCTION
Due to the diversity in mobile communications standards,the concept of software-defined-radio (SDR) has grown major importance. Key advantages of SDR include shorter terminal development cycles and greater debugging capabilities. The ability to adopt new standard features by updating the RFIC controller firmware is a crucial advantage. Reusing configurable blocks like an, e.g. fully programmable FIR filter, for different standards reduces the needed silicon area and thus costs. Another major issue are strong market demands for 2G/3G capable RFICs at costs comparable to current 2G solutions.
This project trade-offs and design considerations for a fully configurable receive DFE aimed at GSM-EDGE, IS-95, and the UMTS frequency division duplex mode (FDD) communication system. The architecture of the ideal software-defined-radio receiver with a minimum of analog components.Due to the excessive requirements on the ADC specification in terms of sampling rate and dynamic range requirements, the direct RF sampling architecture depicted does not seem to be a technical feasible solution.Even if the ADC sampling rate is chosen commensurate for a subsampling architecture the resulting ADC clock jitter performance is extremely difficult to achieve.
Due to the diversity in mobile communications standards,the concept of software-defined-radio (SDR) has grown major importance. Key advantages of SDR include shorter terminal development cycles and greater debugging capabilities. The ability to adopt new standard features by updating the RFIC controller firmware is a crucial advantage. Reusing configurable blocks like an, e.g. fully programmable FIR filter, for different standards reduces the needed silicon area and thus costs. Another major issue are strong market demands for 2G/3G capable RFICs at costs comparable to current 2G solutions.
This project trade-offs and design considerations for a fully configurable receive DFE aimed at GSM-EDGE, IS-95, and the UMTS frequency division duplex mode (FDD) communication system. The architecture of the ideal software-defined-radio receiver with a minimum of analog components.Due to the excessive requirements on the ADC specification in terms of sampling rate and dynamic range requirements, the direct RF sampling architecture depicted does not seem to be a technical feasible solution.Even if the ADC sampling rate is chosen commensurate for a subsampling architecture the resulting ADC clock jitter performance is extremely difficult to achieve.
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