INTRODUCTION
Due to the low-cost and high-data-rate, the popularity of IEEE 802.11-based Wireless Local Area Networks (WLAN) is growing exponentially. There are three major physical layer standards available in the 802.11 family: the Complementary Code Keying (CCK)-based 802.11b , the Orthogonal Frequency Division Multiplex (OFDM)-based 802.11a , and the OFDM-based 802.11g The 802.11b standard uses the 2.4GHz band and supports data rates of 1, 2, 5.5, and 11
Mbits/s. The 802.11a standard operates in the 5GHz band with possible data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mbits/s. The 802.11g standard released in 2003 operates in the 2.4GHz band and supports all the data rates defined in the 802.11a and 802.11b standards. For the higher data rates in 802.11a, the 802.11g standard uses the same OFDM technology in 802.11a, while backward compatibility is added to support the lower data rates of 802.11b . To support the high-data-rate requirements in the 802.11a and 802.11g standards, application specific integrated circuits (ASIC) and field programmable gate arrays (FGPA) designs have been used. However, hardware-based implementations often lack of flexibility and the hardware development cycle is onerous. On the other hand, software based implementations enable elegant reuse of silicon area and dramatically reduce time-to-market through software modification, but are typically much slower than hardware implementations based on comparable technologies.
An existing software implementation for a fully-compliant 802.11a full-rate digital baseband transmitter requires the use of a 22- processor array running at a 1.0GHz clock frequency to reach 54Mbits/s performance . Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard , they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.
In this project, a software-based 802.11a digital baseband transmitter implementation on the TI TMS320C64x DSP. The transmitter can operate over all data rates defined in the 802.11a standard and is compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been introduced to explore the parallelism within and between the individual functions of the transmitter to achieve the high-data-rate requirements: 1) parallelizing the scrambler function and 2) concatenating the FEC encoder, puncturing,and interleaver functions. Experimental results show that the optimized software implementation on a single C64x DSP with a clock frequency of 1.0GHz can operate at a maximum of 136Mbits/s, which is twice as fast as the software implementation in at the same clock frequency.
Due to the low-cost and high-data-rate, the popularity of IEEE 802.11-based Wireless Local Area Networks (WLAN) is growing exponentially. There are three major physical layer standards available in the 802.11 family: the Complementary Code Keying (CCK)-based 802.11b , the Orthogonal Frequency Division Multiplex (OFDM)-based 802.11a , and the OFDM-based 802.11g The 802.11b standard uses the 2.4GHz band and supports data rates of 1, 2, 5.5, and 11
Mbits/s. The 802.11a standard operates in the 5GHz band with possible data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mbits/s. The 802.11g standard released in 2003 operates in the 2.4GHz band and supports all the data rates defined in the 802.11a and 802.11b standards. For the higher data rates in 802.11a, the 802.11g standard uses the same OFDM technology in 802.11a, while backward compatibility is added to support the lower data rates of 802.11b . To support the high-data-rate requirements in the 802.11a and 802.11g standards, application specific integrated circuits (ASIC) and field programmable gate arrays (FGPA) designs have been used. However, hardware-based implementations often lack of flexibility and the hardware development cycle is onerous. On the other hand, software based implementations enable elegant reuse of silicon area and dramatically reduce time-to-market through software modification, but are typically much slower than hardware implementations based on comparable technologies.
An existing software implementation for a fully-compliant 802.11a full-rate digital baseband transmitter requires the use of a 22- processor array running at a 1.0GHz clock frequency to reach 54Mbits/s performance . Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard , they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.
In this project, a software-based 802.11a digital baseband transmitter implementation on the TI TMS320C64x DSP. The transmitter can operate over all data rates defined in the 802.11a standard and is compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been introduced to explore the parallelism within and between the individual functions of the transmitter to achieve the high-data-rate requirements: 1) parallelizing the scrambler function and 2) concatenating the FEC encoder, puncturing,and interleaver functions. Experimental results show that the optimized software implementation on a single C64x DSP with a clock frequency of 1.0GHz can operate at a maximum of 136Mbits/s, which is twice as fast as the software implementation in at the same clock frequency.
1 comment:
Thank you, that was extremely valuable and interesting...I will be back again to read more on this topic.
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