INTRODUCTION
Contour tracing is a method that links connected neighborhood pixels in a binary edge frame, whereas contour filling fills the area inside a contour with a specific integer value, uniquely labeling each objects in an image. Contour tracing and filling are a fundamental element in many video and image processing applications such as video surveillance, medical image processing, computer vision and pattern recognition. Recently, solutions for robust contour tracing and filling methods have been considerably investigated using the state of the-art general purpose sequential processors.
However, these software-based implementations are too slow to archive real-time performance due to the high computational and memory bandwidth inherently required in contour tracing and filling algorithms. As such, an efficient hardware acceleration is inevitable. Although traditional full custom Application Specific Integrated Circuits (ASICs) provide high performance with low power and area, they suffer from flexibility, longer development time and expensive engineering cost.
In contrast, emerging FPGAs with embedded multipliers, memory blocks and high pin counts, are increasingly employed on hardware platforms in many signal/video processing applications. In this project, a proposed real-time, scalable and compact FPGA-based architecture for contour analysis. We utilize the FPGA heterogeneous resources efficiently, and employ advanced design techniques such as heavy pipelining and data parallelism to achieve high throughput but minimizing area and power dissipation.
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