INTRODUCTION
Cryptographic hash functions are ubiquitous algorithm used in numerous schemes like digital signatures, public-key encryption, or MAC's. Hash functions process an arbitrary-length message to produce a small fixed-length digital fingerprint, and should satisfy a variety of security properties (preimage resistance, collision resistance, pseudorandomness, etc.). In the last years, a wide range of attacks have been applied to the previous standards MD5 and SHA-1, to break their collision resistance . Although only collisions in reduced versions of the current standard SHA-2 are known , researchers are skeptical about its long-term security. As a response, the U.S. National Institute of Standards and Technologies (NIST) recently launched a call for candidate functions for a new cryptographic hash algorithm (SHA-3) family . The hash functions MD6 (by the author of MD5) and ïrRUPT have been accepted as Round 1 candidates. Besides a high security, the new hash standard should be suitable for implementations on a wide range of applications. In particular, hardware efficiency will be crucial to determine the future SHA-3, because hardware resources are often limited, whereas on high-end PC's it does not matter much in general; indeed, even the slowest hash function has acceptable performance on a PC. Furthermore, hash function designers seldom study the hardware performance. It is thus necessary to independently study implementations of future candidates on ASIC and FPGA, and determine their suitability for resource limited environments.
This project presents a hardware architectures for the hash functions MD6 and ïrRUPT. Particular attention has been drawn in the analysis of the round process to exploit parallelism, to maximize the circuit speed.
Cryptographic hash functions are ubiquitous algorithm used in numerous schemes like digital signatures, public-key encryption, or MAC's. Hash functions process an arbitrary-length message to produce a small fixed-length digital fingerprint, and should satisfy a variety of security properties (preimage resistance, collision resistance, pseudorandomness, etc.). In the last years, a wide range of attacks have been applied to the previous standards MD5 and SHA-1, to break their collision resistance . Although only collisions in reduced versions of the current standard SHA-2 are known , researchers are skeptical about its long-term security. As a response, the U.S. National Institute of Standards and Technologies (NIST) recently launched a call for candidate functions for a new cryptographic hash algorithm (SHA-3) family . The hash functions MD6 (by the author of MD5) and ïrRUPT have been accepted as Round 1 candidates. Besides a high security, the new hash standard should be suitable for implementations on a wide range of applications. In particular, hardware efficiency will be crucial to determine the future SHA-3, because hardware resources are often limited, whereas on high-end PC's it does not matter much in general; indeed, even the slowest hash function has acceptable performance on a PC. Furthermore, hash function designers seldom study the hardware performance. It is thus necessary to independently study implementations of future candidates on ASIC and FPGA, and determine their suitability for resource limited environments.
This project presents a hardware architectures for the hash functions MD6 and ïrRUPT. Particular attention has been drawn in the analysis of the round process to exploit parallelism, to maximize the circuit speed.
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