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VLSI IEEE 2018 Projects at Chennai

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An Efficient Architecture for 3-D Discrete Wavelet Transform

An Efficient Architecture for 3-D Discrete Wavelet Transform

Abstract-This project presents an architecture of the lifting based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput. The proposed architecture has been designed using Verilog HDL with Matlab and Simulated using Modelsim/Matlab Softwares.The input videos are converted as frames using Matlab and corresponding pixel values are stored.3D-DWT architectures is developed using Verilog HDL and even number of frame are taken as input to DWT.

Fig. Spatio-temporal wavelet decomposition with proposed architecture. (a) Original frame sequence. (b) After 1 level spatial transform. (c) Lowpass frames after the temporal transform. (d) Highpass frames after the temporal transform.

Simulation Video Demo 

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