Visit our new YouTube channel exclusively for Matlab Projects and Electrical Project @,YouTube-Matlab Projects YouTube-Electrical Projects

VLSI IEEE 2018 Projects at Chennai

Looking for VLSI 2018 Projects,Click Here or Contact @ +91 9894220795/+9144 42647783.For more details visit



  • DCT-Based Image Watermarking Using Subsampling- Verilog with Matlab
  • VLSI Implementation of Invisible Digital Watermarking Algorithms- Verilog with Matlab
  • An FPGA-based Architecture for Real Time Image Feature Extraction- Verilog with Matlab
  • Contrast Enhancement of Color Images using Tunable Sigmoid Function- Verilog with Matlab
  • Robust DWT-SVD Domain Image Watermarking Embedding Data in All Frequencies
  • Shift Invert Coding (SINV) for Low Power VLSI
  • VLSI Implementation of Discrete Wavelet Transform (DWT) and IDWT for Image Compression- Verilog with Matlab
  • A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)- Verilog with Matlab
  • Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
  • Visual Attention Driven Image to Video Adaptation- Verilog with Matlab
  • A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
  • A Verilog Implementation of UART Design with BIST Capability
  • An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing
  • Image Compression with Different Types of Wavelets- Verilog with Matlab
  • A Low-Power Multiplier With the Spurious Power Suppression Technique
  • A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier
  • Design and Implementation of a low complexity real lossless Image compression method for wireless endoscopy capture system- Verilog with Matlab
  • Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
  • Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
  • Low-power and high-quality Cordic-based Loeffler DCT for signal processing
  • Low-Power Built-In Logic Block Observer Realization for BIST Applications-VHDL
  • Video Adaptation for Small Display Based on Content Recomposition- Verilog with Matlab
  • VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application
  • A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
  • FPGA Based Design of a Novel Enhanced Error Detection And Correction Technique
  • FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications
  • FPGA Implementation of a Scalable Encryption Algorithm
  • Fuzzy based PID Controller using Verilog HDL for Transportation Application
  • Implementation of 64 Point FFT using Vedic Multiplier
  • Implementation of IEEE 802.11 a WLAN Baseband Processor
  • Multiplier design based on ancient Indian vedic muliplier
  • Research on Fast Super-resolution Image Reconstruction Base on Image Sequence-Verilog with Matlab
  • VLSI Implementation of an Edge-Oriented Image Scaling Processor- Verilog with Matlab
  • 3D Discrete Wavelet Transform VLSI Architecture for Image Processing- Verilog with Matlab
  • A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
  • An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM- Convolutional Encoders
  • Biometric Encryption using Fingerprint Fuzzy Vault for FPGA-based Embedded Systems- Verilog with Matlab
  • CSI Multimedia Architecture
  • Fast Scaling in the Residue Number System
  • Design and Implementation of Boundary-Scan Circuit
  • FPGA Based Power Efficient Channelizer For Software Defined Radio
  • FPGA-Based Face Detection System Using Haar Classifiers- Verilog with Matlab
  • Hardware Algorithm for Variable Precision Multiplication on FPGA
  • Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL- Verilog with Matlab
  • VLSI Implementations of the Cryptographic Hash Functions MD6
  • FPGA Implementations of the Hummingbird Cryptographic Algorithm
  • A High-speed 32-bit Signed Unsigned Pipelined Multiplier
  • Software-Defined Radio for OFDM Transceivers
  • VLSI Implementation of Fully Pipelined Multiplier less 2D DCT IDCT Architecture for JPEG- Verilog with Matlab
  • Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
  • High Speed and Low Space Complexity FPGA Based ECC
  • FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms- Verilog with Matlab
  • FPGA Implementation of Modular Multiplication methods using Cellular Automata
  • FPGA Implementation of High Performance LDPC Decoder using Modified 2-bit
  • Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
  • Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
  • Coherent Amplitude Modulated QAM-QPSK
  • A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform- Verilog with Matlab
  • A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
  • A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264AVC- Verilog with Matlab
  • A High Performance Binary to BCD Converter for Decimal Multiplication
  • An Efficient Architecture for 3 D Discrete Wavelet Transform-Verilog HDL with Matlab
  • A New Reversible Design of BCD Adder
  • A Multichannel Watermarking DCT-DWT- Verilog with Matlab
  • An Efficient Implementation of Floating Point Multiplier
  • An implementation of a 2D FIR filter using the signed-digit number system- Verilog with Matlab
  • Automatic Road Extraction using High Resolution Satellite Images based on  Mean Shift Method- Verilog with Matlab
  • Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
  • Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor
  • Design and Implementation of APB Bridge based on AMBA 4.0
  • Design and VLSI implementation of high-performance face-detection engine for mobile applications- Verilog with Matlab
  • Design Enhancement of Combinational Neural Networks Using HDL based FPGA Framework for Pattern Recognition- Verilog with Matlab
  • Efficient VLSI Architecture for Discrete Wavelet Transform- Verilog with Matlab
  • FPGA based FFT Algorithm Implementation in WiMAX Communications System
  • FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise Two Approaches- Verilog with Matlab
  • High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
  • Image Encryption Based On AES Key Expansion- Verilog with Matlab
  • Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA- Verilog with Matlab
  • PCFICH Channel Design for LTE using FPGA- Verilog with Matlab
  • Pipelined Architecture for FPGA Implementation of Lifting-Based DWT- Verilog with Matlab
  • A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform- Verilog with Matlab
  • A Region Merging Approach for Image Segmentation on FPGA- Verilog with Matlab
  • An Efficient Viterbi Decoder
  • Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
  • Design of Low Power TPG Using LP-LFSR
  • FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization- Verilog with Matlab
  • HDL Design for Image Segmentation using Gabor filter for Disease Detection- Verilog with Matlab
  • High  Speed and Area Efficient Vedic Multiplier
  • High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers
  • Improved Architectures for a Fused Floating-Point Add-Subtract Unit
  • Low-Power and Area-Efficient Carry Select Adder
  • Low-Power Variation-Aware Flip Flop
  • Modified Architecture for Real-Time Face Detection using FPGA- VHDL with Matlab
  • Very Low Resolution Face Recognition Problem- Verilog with Matlab
  • Viterbi-Based Efficient Test Data Compression
  • VLSI Architecture of Arithmetic Coder Used in SPIHT- Verilog with Matlab
  • FPGA Implementation of MIMO-OFDM STBC Systems-Verilog with Matlab
  • Cordic for Fixed Angle Rotation
  • Design and  Implementation of 32  Bit Unsigned Multiplier Using  CLAA and CSLA
  • Design Of High Speed Floating Point Mac Using Vedic Multiplier And Parallel Prefix Adder
  • Design of High Speed Low Power Multiplier using Reversible logic-a Vedic Mathematical Approach
  • Design of High-speed low power Reversible Logic BCD Adder Using HNG gate
  • Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Techniques for Compensating Memory Errors in JPEG2000- Verilog with Matlab
  • Visible and Infrared Image Fusion using the Lifting Wavelets- VHDL with Matlab
  • VLSI Implementation of an Adaptive Edge -Enhanced Image Scalar for RealTime Multimedia Applications- Verilog with Matlab
  • VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications- Verilog with Matlab
  • Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform Neural Network Architecture-   Verilog with Matlab
  • A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm-Verilog with Matlab
  • Design and simulation of Gabor filter using Verilog HDL-Verilog HDL with Matlab
  • A Distributed Canny Edge Detector Algorithm and FPGA Implementation- Verilog with Matlab
  • A New Secure Image Transmission Technique via Secret-Fragment-Visible Mosaic Images- Verilog with Matlab
  • Design and Implementation of Orthogonal Code Convolution Using Enhanced Error Control Technique
  • FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm
  • High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)
  • SW-HW Implementation of Image Covariance Descriptor For Person Detection Systems
  • VLSI Based Image Zooming Application by a Novel Adaptive Edge Enhancement Technique- Verilog with Matlab
  • Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform-Verilog with Matlab
  • Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay-Verilog with Matlab 
  • ASIC Implementation of Two Stage Pipelined Multiplier 
  • Hardware Software Co-Simulation of Edge Detection for Image Processing System-Verilog with Matlab
  • Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform-Verilog with Matlab
  • An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching-Verilog HDL with Matlab
  • Reviewing High-Radix Signed-Digit Adders 
  • A New-High Speed-Low Power-Carry Select adder Using Modified GDI
  • Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
  • A Modified Partial Product Generator for Redundant Binary Multipliers
  • A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
  • Design and Analysis of Approximate Compressors for Multiplication
  • Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  • Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
  • Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
  • Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
  • A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
  • A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications- Verilog HDL
  • High Performance VLSI Architecture for 3-D Discrete Wavelet Transfor-Verilog HDL with Matlab
  • A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
  • A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT
  • High-Speed and Low-Latency ECC Processor Implementation Over GF(2m)on FPGA
  • Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
  • LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
  • Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
  • On Efficient Retiming of Fixed-Point Circuits
  • Hybrid LUT/Multiplexer FPGA Logic Architectures
  • Concept, Design, and Implementation of Reconfigurable CORDIC 
  • Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
The above listed topics are just for reference. If you have any new Ideas/Papers send to us at or Call +91 98942 20795

No comments: