Design and VLSI implementation of an address generation coprocessor

Introduction

Modern general purpose VLSI processors are designed for high average performance for a wide range of applications. However, the efficient solution of some tasks demands the enhancement of the processing capabilities of the processor (e.g. floating point computations). In spite of the advances in microelectronic technology, the addition of functional units to the VLSI processor is restricted by the limited amount of real estate available. A viable alternative for increasing computer performance is based on the use of special purpose units which take some of the computation burden from the main processor.

Floating-point processors, CRT controllers, disk controller and DMA controllers, are but a few examples of currently available devices. In some cases, these units are designed to perform certain restricted data processing tasks in a very efficient manner. In other cases, they help in the management of the computer system resources. For example, memory management units (MMUs) assist the main processor in controlling the elements of the memory hierarchy of a computer system, which consists of a cache, primary storage and secondary storage. Most present-day computer applications are developed using structured high level languages (HLLs) such as Pascal, Ada etc. In an HLL, information is generally handled in a structured form, e.g. as procedures and data structures. In general, HLL compilers will generate a considerable amount of code just to navigate through the data structures. This aggravates the problem of the addressing overhead. 

Efficient address generation for data structures is therefore a primary goal in obtaining high performance in a computer system. This is particularly true in a reduced instruction set computer (RISC) environment where the address calculations are almost exclusively performed in software since the available addressing modes in a RISC machine are limited. Another area where address computation is important is that of digital signal processing (DSP). Significant effort has been focused on the design of special purpose processors .

Nwachukwu has proposed an array indexing unit for address generation in an array processor to produce a system which is more versatile than conventional fast Fourier transform (FFT) array processors. Instead of building special purpose architectures, some designers have concentrated their efforts on using general purpose processors to achieve versatility at the expense of having to generate addresses in software. One example is the fast Fourier transform algorithm and its many variations . Although these algorithms improve the efficiency of the various DSP operations, a significant amount of time is wasted in address calculations since a general purpose processor is used.

In this Project a hardware unit that is tailored to function more efficiently with data structures associated with DSP applications. This device can be viewed as either a memory reconfiguring unit (MRU) or as a coprocessor for accomplishing address transformations. The objective is to design an MRU which is easy to interface between the host processor and memory and which would not require any modifications either to the host processor or the memory. Special opcodes have not been introduced into the instruction repertoire nor does the design presume any modifications to the existing operating system. 

The function of a unit such as the MRU is to provide the CPU with a set of specialised addressing modes as defined by algorithms which are frequently used in several major applications. Then the details of the VLSI implementation of the MRU are presented. The Octtools tool suite* is used for the design. The feasibility of a VLSI implementation is thus demonstrated. Finally, the performance of MRU is evaluated using popular signal processing algorithms such as convolution, correlation, FFT etc. These algorithms are selected because they utilise different address sequences. The performance of a computer system with the MRU and one without the MRU are evaluated to illustrate the speed factor contributed by the MRU.