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Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths


Power dissipation is one of the major design constraints for modem very large scale integration (VLSI) circuits due to the continuing increase in chip density. While many techniques have investigated power minimization during the normal (functional) mode of operation, an emerging research area is power minimization during test application. Low power testing is important to increase reliability and yield of the circuit under test. Previous work has addressed power minimization during test application at logic and system level. At logic level for combinational circuits employing built-in self-test (BIST) several techniques for minimizing power dissipation have been proposed recently . 

In the use of dual speed linear feedback shift register (LFSR) lowers the transition density at the circuit inputs leading to minimized power dissipation.  Optimal weight sets for input signal distribution aredetermined in order to minimize average power , while the peak power is reduced by finding the best initial conditions in the cellular automata (CA) cells used for pattern generation . It has been proved in that all the primitive polynomial LFSR of the same size, produce the same power dissipation in the circuit under test, thus advising to use the LFSR with smaller number of XOR gates since it yields lowest power dissipation by itself. A mixed solution based on reseeding LFSRs and test vector inhibiting to filter non-detecting subsequences of a pseudorandom test sequence has been proposed . An enhancement of test vector inhibiting technique has been proposed in  where all the non-detecting subsequences are filtered. 

A different approach for filtering non-detecting vectors inspired by the precomputation architecture is present. An improvement in area overhead associated with filtering nondetecting vectors without penalty in fault coverage or test length has been achieved using non-linear hybrid cellular automata. Regardless of the type of test pattern generator, BIST architectures significantly differ one from another in terms of power dissipation as outlined. Thus, circuit partitioning for low power BIST and test session planning have an important influence on power dissipation.Regularity of multiplier modules and linear sized test set required to achieve high fault coverage lead to efficient low power BIST implementations.To minimize power dissipation in scan-BIST sequential circuits during test application numerous techniques have been proposed. 

To minimize shifting power dissipation, test vector inhibiting techniques proposed for combinational circuits are extended to scan sequential circuits. In the test vector inhibiting technique is extended where the modules and modes with the highest power dissipation are identified, and gating logic has been introduced to reduce power dissipation. Despite substantial savings in power dissipation vector detection and gating logic introduce not only area overhead but also the low transition random test pattern generator (LT-RTPG) proposed, neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation has been proposed. 

It should be noted that techniques proposed for reducing power dissipation in standard scan design for test (DFT) methodology  can equally be applied to scan-BIST environment subject to minor modifications. While techniques for power minimization at logic level yield modest savings they can be combined with techniques proposed  at higher levels of abstraction to produce further savings in power dissipation. Furthermore, new techniques for power minimization at higher levels of abstraction are required when applying BIST for register-transfer level (RTL) data paths synthesized using high level synthesis
for low power.

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