Visit our new YouTube channel exclusively for Matlab Projects and Electrical Project @,YouTube-Matlab Projects YouTube-Electrical Projects

VLSI IEEE 2018 Projects at Chennai

Looking for VLSI 2018 Projects,Click Here or Contact @ +91 9894220795/+9144 42647783.For more details visit


Low-Power Digit-Based Reconfigurable FIR Filter


FINITE-impulse response (FIR) filters play a crucial role in many signal processing applications in communication systems. A wide variety of tasks such as spectral shaping, matched filtering, interference cancellation, channel equalization, etc. can be performed with these filters. Hence, various architectures and implementation methods have been proposed to improve the performance of filters in terms of speed and complexity. Recently, explosive proliferation in wired and wireless communication standards renders traditional FIR architectures less suitable for future communication needs. 

On the other hand, software radio has gained much attention from the researchers worldwide due to a strong demand for reconfigurable communication systems capable of multi-standard operations.In light of this trend, programmability and reconfigurability need be taken into account in filter architecture design. It is well known that the canonical signed digit (CSD) representation can be used to reduce the complexity of FIR digital filter implementation . Encoding the filter coefficients using the CSD representation reduces the number of partial products and thus saves silicon area and power consumption in hardware implementation. 

Hence, this technique is popular for fixed-coefficient FIR filter implementation. When applying the CSD representation to implementing programmable, rather than fixed-coefficient, FIR filters, it is natural to require that the number of programmable CSDs in a coefficient be fixed. However, for most filters, only a few taps require high-precision coefficients. Valuable hardware resources are wasted if all taps are implemented with the highest precision. To minimize hardware complexity, there have been several works on programmable FIR filter implementation and they all limit the number of allowable nonzero CSDs in every tap . Unfortunately, this restriction can lower the coefficient precision and degrade the frequency response of the filter or it can induce a large overhead by assigning more CSDs than necessary to most taps. 

Another hardware-efficient implementation of programmable FIR filters with CSD coefficients. A 32-tap linear-phase filter, with two nonzero CSDs in each tap, is implemented. Additional nonzero CSDs can be allocated to specific filter taps, making it a reconfigurable FIR filter architecture. Nevertheless, some computational resources may still be unused and the critical path is quite long in some cases. Due to a wide range in the filter coefficient precision for different applications, it is next to impossible to achieve reconfigurability without incurring overhead in hardware. As an example, a binary pseudorandom number (PN) code matched filter, which is an important block in CDMA receivers, requires only 1-bit coefficient precision while a pulse-shaping filter may require as high a coefficient precision as 16 bits. Since the tap complexity in these two cases can be very different, the tapbased reconfigurable FIR filter is quite inefficient. 

In this brief, we adopt the finest granularity for filter implementation and propose a reconfigurable FIR filter architecture with extreme flexibility.With this architecture, both the tap number and the number of nonzero digits in each tap can be arbitrarily assigned given that enough hardware resource is available. Techniques that yield an FIR filter with the minimum total number of CSD for a given frequency response .

No comments: