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Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor


The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate:
1) parallelizing the scrambler function and
2) concatenating the FEC encoder, puncturing, and inter leaver functions.

Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.


The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel.

Table 1 lists the mode-dependent parameters for the 802.11a standard.
The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol.

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