INTRODUCTION
One of the most challenging test stands for wearable computer and remote sensor systems is the transmission of images. In fact, the amount of memory needed for the storage of color video images and the high speed required for their transmissions make the performance/ cost tradeoff difficult to attain. As a consequence, compression techniques are mandatory to sensibly reduce the amount of data needed for frame transmission. As far as static images are concerned,1 the best performance and compression rates are obtained by lossy algorithms, such as JPEG or JPEG2000. However, specific applications may prefer low-complex lossless schemes, especially if the quality of the transmitted image is a mandatory constraint. Among all others, Lossless JPEG , FELICS, and CALIC are few examples of lossless compression algorithms, but the coding scheme that features the best complexity/compression rate tradeoff is LOCO-I (low complexity lossless compression for images), the core of the JPEG-LS standard.
In this project, we present an efficient implementation of the LOCO-I algorithm tailored for field-programmable gate-array (FPGA) applications. The design takes fully advantage of the sequential nature of the LOCO-I compression scheme and results into a pipelined architecture for both encoder and decoder circuits. Consequently, significant performance improvements can be obtained with respect to previous nonpipelined designs without modifying the original compression scheme.
One of the most challenging test stands for wearable computer and remote sensor systems is the transmission of images. In fact, the amount of memory needed for the storage of color video images and the high speed required for their transmissions make the performance/ cost tradeoff difficult to attain. As a consequence, compression techniques are mandatory to sensibly reduce the amount of data needed for frame transmission. As far as static images are concerned,1 the best performance and compression rates are obtained by lossy algorithms, such as JPEG or JPEG2000. However, specific applications may prefer low-complex lossless schemes, especially if the quality of the transmitted image is a mandatory constraint. Among all others, Lossless JPEG , FELICS, and CALIC are few examples of lossless compression algorithms, but the coding scheme that features the best complexity/compression rate tradeoff is LOCO-I (low complexity lossless compression for images), the core of the JPEG-LS standard.
In this project, we present an efficient implementation of the LOCO-I algorithm tailored for field-programmable gate-array (FPGA) applications. The design takes fully advantage of the sequential nature of the LOCO-I compression scheme and results into a pipelined architecture for both encoder and decoder circuits. Consequently, significant performance improvements can be obtained with respect to previous nonpipelined designs without modifying the original compression scheme.
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