IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY

INTRODUCTION

Manufacturing processes are extremely complex, inducing manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built-In-Self-Test (BIST). A BIST Universal Asynchronous Receive/Transmit (UART) has the objectives of firstly to satisfy specified testability requirements, and secondly to generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. Although BIST techniques are becoming more common in industry, the additional BIST circuit that increases the hardware overhead increases design time and performance degradation is often cited as the reason for the limited use of BIST .

This project focuses on the design of a UART chip with embedded BIST architecture using Field Programmable Gate Array (FPGA) technology. The paper describes the problems of Very-Large-Scale-Integrated (VLSI) testing followed by the behavior of UART circuit using Verilog Hardware Description Language . In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements. The UART is targeted at broadband modem, base station, cell phone, and PDA designs.

VERILOG AND BIST

It is increasingly common for design for testability (DFT) issues to be addressed at design reviews prior to circuit tapeout approval. Previously, in the age of schematics, this often requires design and test engineers to sift through pages of manuals and data sheets looking for things like asynchronous set/reset circuit configurations, derived or internally generated clocks, and combinatorial and sequential feedback loops. The review inevitably occurred late in the design cycle; adversely affecting project schedules if glitches were found, and making for an uncomfortable process for the circuit designer. However, with today's design practices, schematics are mostly outdated. Designers can take more control of the DFT review by performing DFT rule checking at the register transfer language (RTL) (Verilog) level. Nevertheless, finding DFT problems in language-based designs is still not a simple task for humans.

The acceptance of the design for test techniques has been largely due to the possibility of Verilog support to this design style. It is desirable to eventually have available a BIST approach with similarly Verilog support. The high degree of standardization makes it possible to have most testability feature previously added to a design using Verilog 

UART

A universal asynchronous receiver/transmitter is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with other communication standards such asRS-232.

A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART or DUART combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs.