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Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability.

Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of an FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.


The ever-increasing demand for mobile and portable communication requires high-performance systems employing advanced signal processing techniques to allow operation as close as possible to the Shannon information theoretic bound. However,not only must these systems provide exceptional performance, but due to market and fiscal pressures, they must be flexible enough to allow the rapid tracking of evolving and fluid standards. Software defined radios (SDRs) are emerging as a viable solution for meeting the conflicting demands in this arena. SDRs support multimode and multiband modes of operation to allow service providers an economic means of futureproofing these increasingly complex and costly systems.

During the last decade or so, radio system functionality has migrated from analog to digital implementations. We have observed, and continue to observe, the migration of the digital portion of a receiver along the signal conditioning chain, moving ever closer to the antenna. The implementation of these high-performance digital communication systems has been made possible by advances in semiconductor process technology, that has allowed the concept of system on a chip to become a reality.

In a communication environment the hardware platform must execute sophisticated source coding algorithms, modulation, demodulation, power control, channel coding, multiple access (TDMA, FDMA, CDMA) schemes and many levels of synchronization, starting at the physical layer, and moving up through the open system interconnection (OSI) protocol stack.

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