When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check , others are designed to detect as well as correct errors, such as Salomon Codes. However, the existing techniques are not able to achieve high efficiency and to meet bandwidth requirements, especially with the increase in the quantity of data transmitted.
Orthogonal Code is one of the codes that can detect errors and correct corrupted data. Our objective in this paper is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.
Orthogonal codes are binary valued and they have equal number of 1’s and 0’s. An n-bit orthogonal code has n/2 1’s and n/2 0’s; i.e., there are n/2 positions where 1’s and 0’s differ . Therefore, all orthogonal codes will generate zero parity bits. The concept is illustrated by means of an 8- bit orthogonal code as shown in Fig.1. It has 8-orthogonal codes and 8-antipodal codes for a total of 16-biorthogonal codes. Antipodal codes are just the inverse of orthogonal codes; they are also orthogonal among themselves.