INTRODUCTION
TRADEOFF between system performance and power dissipation is one of the most critical issues in the design of a wireless portable device. Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multirate sampling the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm to yield a symbol-rate signal stream for data decoding. This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.
To enable power reduction with symbol-rate sampling, both Mueller–Muller detection (MMD) and MMD-based timing recovery methods have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing synchronization issue in orthogonal frequency-division multiplexing (OFDM) systems based on the best block-boundary search for each fast Fourier transform (FFT) window.
Accordingly, multirate sampling,schemes have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation. To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sampletiming control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multirate sampling methods, this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC for low-power wireless applications.
TRADEOFF between system performance and power dissipation is one of the most critical issues in the design of a wireless portable device. Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multirate sampling the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm to yield a symbol-rate signal stream for data decoding. This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.
To enable power reduction with symbol-rate sampling, both Mueller–Muller detection (MMD) and MMD-based timing recovery methods have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing synchronization issue in orthogonal frequency-division multiplexing (OFDM) systems based on the best block-boundary search for each fast Fourier transform (FFT) window.
Accordingly, multirate sampling,schemes have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation. To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sampletiming control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multirate sampling methods, this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC for low-power wireless applications.
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