Introduction
Field Programmable Gate Arrays (FPGAs) have been widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high speed telecommunication chips. FPGAs are suitable for prototypes of systems whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA. The frequent reconfiguration of an FPGA makes it more fault-prone.There are many components of an FPGA to test for ensuring reliable usage of this device.
In this projecy, we only consider test of LEs and focus on LUTs within LEs. There are different methods for LE testing. One may use I/O pins for applying test vectors to LEs and collecting test results. But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable . A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing, which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs. Our objective is to propose a BIST architecture with a good balance between various costs. Test time, test area and granularity are such trade-offs.
Field Programmable Gate Arrays (FPGAs) have been widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high speed telecommunication chips. FPGAs are suitable for prototypes of systems whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA. The frequent reconfiguration of an FPGA makes it more fault-prone.There are many components of an FPGA to test for ensuring reliable usage of this device.
In this projecy, we only consider test of LEs and focus on LUTs within LEs. There are different methods for LE testing. One may use I/O pins for applying test vectors to LEs and collecting test results. But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable . A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing, which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs. Our objective is to propose a BIST architecture with a good balance between various costs. Test time, test area and granularity are such trade-offs.
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