Cordic based Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

Cordic based Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

Abstract—Fast Fourier transform (FFT) co-processor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot product- add (FDPA) unit, to compute AB ± CD ±E, based on binary signed- digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The design is developed based on Cordic Algorithm using Floating Point Butterfly.The result results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area. 

FFT butterfly architecture with expanded complex numbers

A butterfly architecture using redundant FP arithmetic, which is useful for FP FFT co-processors and

contributes to digital signal processing applications. Although there are other works on the use of redundant FP number systems, they are not optimized for butterfly architecture in which both redundant FP multiplier and adder are required. The novelties and techniques used in the proposed design include the following.
1) All the significands are represented in binary signed digit (BSD) format and the corresponding carry-limited adder is designed.
2) Design of FP constant multipliers for operands with BSD significands.
3) Design of FP three-operand adders for operands with BSD significands.
4) Design of FP fused-dot-product-add (FDPA) units (i.e., AB ± CD ± E) for operands with BSD significands.

Simulation Video Demo