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Dynamic Random Access Memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this work, investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer and a distribution of data-retention times, in steps our algorithm computes refresh periods that minimize DRAM dissipation, where is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.


In this section, describe the hardware implementation of BM. Due to process variations, every memory will have different leakage current distribution. Hence, to guarantee maximum power reduction for every memory, the refresh signal generator must be programmable. Following figure describes a possible implementation of the refresh signal generator. It is composed of  K-1 counters of programmable period to generate K-1 additional refresh periods, added to the original period generated from the refresh address counter. The counters are incremented each time the refresh address counter completes a cycle, thus generating integral multiples of the original period. The cycle period of each counter can be programmed to one of the added periods by programming its reset condition. This is accomplished by connecting an output of the d:d2 decoder, which is asserted once every period, to the counter reset by means of fuses. The output of the refresh signal generator is a K-bit signal indicating whether the current cycle is the programmed period or not for the counters.

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