A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE

Introduction

This project describes a novel architecture of Universal Asynchronous Receiver Transmitter (UART) based on Recursive Running Sum (RRS) filter. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The robust UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one third of required bit period. The intermediate data bit is decoded using magnitude comparator. A majority voter is used to decode actual data bit from three intermediate data bits.

Universal Asynchronous Receiver Transmitter (UART) is used for asynchronous serial data communication between remote embedded systems. Standard UART cores three mid-bit samples to decode the serial data bit and the sampling rate is derived from external timer module. But if the physical channel is noisy then data bits get corrupted during transmission and it leads to wrong data decoding at receiver. To overcome the noise problem a digital low pass filter based architecture is proposed in this project.

Recursive Running Sum (RRS) is simple low pass filter, it can be used to remove noise samples from data samples at receiver .Serial receive data signal is directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable and it decides baud rate. The robust UART core can be designed using Verilog HDL and can be implemented on Xilinx/ALTERA FPGA .

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